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cop888fh 8-bit cmos rom based microcontrollers with 12k memory, comparators, usart and hardware multiply/divide general description the cop888fh family of rom based microcontrollers are highly integrated cop8 ? feature core devices with 12k memory and advanced features including analog compara- tors, and hardware multiply/divide. these single-chip cmos devices are suited for more complex applications re- quiring a full featured controller, low emi, two comparators, a full-duplex usart, and hardware multiply/divide functions. cop87l88fh devices are pin and software compatible (dif- ferent v cc range) 16k otp (one time programmable) ver- sions for pre-production , and for use with a range of cop8 software and hardware development tools. family features include an 8-bit memory mapped architec- ture, 10 mhz cki with 1s instruction cycle, hardware multiply/divide functions, three multi-function 16-bit timer/ counters with pwm, full duplex usart, microwire/ plus ? , two analog comparators, two power saving halt/ idle modes, miwu, idle timer, high current outputs, software selectable options watchdog ? and clock/ oscillator mode, low emi 2.5v to 5.5v operation, and 28/ 40/44 pin packages. devices included in this data sheet are: device memory (bytes) ram (bytes) i/o pins packages temperature comments cop684fh 12k rom 512 24 28 dip/soic -55 to +125c 4.5v to 5.5v cop884fh 12k rom 512 24 28 dip/soic -40 to +85c cop984fh 12k rom 512 24 28 dip/soic 0 to +70c 2.5v to 4.0v, fhh=4.0v to 6.0v cop688fh 12k rom 512 36/40 40 dip, 44 plcc -55 to +125c 4.5v to 5.5v cop888fh 12k rom 512 36/40 40 dip, 44 plcc -40 to +85c cop988fh 12k rom 512 36/40 40 dip, 44 plcc 0 to +70c 2.5v to 4.0v, fhh=4.0v to 6.0v key features n hardware multiply/divide functions n full duplex usart n three 16-bit timers, each with two 16-bit registers supporting: e processor independent pwm mode e external event counter mode e input capture mode n quiet design (low radiated emissions) n 12 kbytes on-board rom n 512 bytes on-board ram additional peripheral features n idle timer n multi-input wakeup (miwu) with optional interrupts (8) n two analog comparators n watchdog and clock monitor logic n microwire/plus serial i/o i/o features n software selectable i/o options ( tri-state ? , push-pull, weak pull-up, and high impedance input) n schmitt trigger inputs on ports g and l n packages: e 40 dip with 36 i/o pins e 44 plcc with 40 i/o pins e 28 dip/so with 24 i/o pins cpu/instruction set features n 1 s instruction cycle time n fourteen multi-source vectored interrupts servicing e external interrupt e idle timer t0 e three timers (each with 2 interrupts) e microwire/plus e multi-input wake up e software trap e usart (2) e default vis (default interrupt) n versatile and easy to use instruction set cop8 ? is a trademark of national semiconductor corporation. microwire ? is a trademark of national semiconductor corporation. microwire/plus ? is a trademark of national semiconductor corporation. tri-state ? is a registered trademark of national semiconductor corporation. watchdog ? is a trademark of national semiconductor corporation. icemaster ? is a trademark of metalink corporation. september 1999 cop888fh 8-bit cmos rom based microcontrollers with 12k memory, comparators, usart and hardware multiply/divide ? 2000 national semiconductor corporation ds012602 www.national.com
cpu/instruction set features (continued) n 8-bit stack pointer (sp) e stack in ram n two 8-bit register indirect data memory pointers (b and x) fully static cmos n low current drain (typically < 5 a) n two power saving modes: halt and idle n single supply operation: 2.5v5.5v n temperature ranges: 0c to +70c, ?40c to +85c ?55c to +125c development support n emulation and otp devices n real time emulation and full program debug offered by metalink development system block diagram ds012602-1 figure 1. cop888fh block diagram cop888fh www.national.com 2
connection diagrams plastic chip carrier ds012602-2 top view order number cop688fh-xxx/v, cop888fh-xxx/v or cop988fh-xxx/v see ns plastic chip package number v44a dual-in-line package ds012602-3 top view order number cop688fh-xxx/n, cop888fh-xxx/n or cop988fh-xxx/n see ns molded package number n40a dual-in-line package ds012602-4 order number cop684fh-xxx/m, cop884fh-xxx/m, cop984fh-xxx/m, cop684fh-xxx/n, cop884fh-xxx/n or cop984fh-xxx/n see ns molded package number m28b or n28b figure 2. connection diagrams cop888fh www.national.com 3
connection diagrams (continued) pinouts for 28-, 40- and 44-pin packages port type alt. fun alt. fun 28-pin 40-pin 44-pin pack. pack. pack. l0 i/o miwu 11 17 17 l1 i/o miwu ckx 12 18 18 l2 i/o miwu tdx 13 19 19 l3 i/o miwu rdx 14 20 20 l4 i/o miwu t2a 15 21 25 l5 i/o miwu t2b 16 22 26 l6 i/o miwu t3a 17 23 27 l7 i/o miwu t3b 18 24 28 g0 i/o int 25 35 39 g1 wdout 26 36 40 g2 i/o t1b 27 37 41 g3 i/o t1a 28 38 42 g4 i/o so 1 3 3 g5 i/o sk 2 4 4 g6isi 355 g7 i/cko halt restart 4 6 6 d0o 192529 d1o 202630 d2o 212731 d3o 222832 d4 o 29 33 d5 o 30 34 d6 o 31 35 d7 o 32 36 i0i 799 i1 i comp1in? 8 10 10 i2 i comp1in+ 9 11 11 i3 i comp1out 10 12 12 i4 i comp2in? 13 13 i5 i comp2in+ 14 14 i6 i comp2out 15 15 i7 i 16 16 c0 i/o 39 43 c1 i/o 40 44 c2 i/o 1 1 c3 i/o 2 2 c4 i/o 21 c5 i/o 22 c6 i/o 23 c7 i/o 24 v cc 688 gnd 23 33 37 cki 5 7 7 reset 24 34 38 cop888fh www.national.com 4
cop98xfh absolute maximum ratings (note 1) if military/aerospace specified devices are required, please contact the national semiconductor sales office/ distributors for availability and specifications. supply voltage (v cc )7v voltage at any pin ?0.3v to v cc + 0.3v total current into v cc pin (source) 100 ma total current out of gnd pin (sink) 110 ma storage temperature range ?65c to +140c note 1: absolute maximum ratings indicate limits beyond which damage to the device may occur. dc and ac electrical specifications are not ensured when operating the device at absolute maximum ratings. dc electrical characteristics cop98xfh: 0c t a +70c unless otherwise specified parameter conditions min typ max units operating voltage cop98xfh 2.5 4.0 v cop98xfhh 4.0 6.0 v power supply ripple (note 2) peak-to-peak 0.1 v cc v supply current (note 3) cki = 10 mhz v cc = 5.5v, t c = 1 s 12.5 ma cki = 4 mhz v cc = 5.5v, t c = 2.5 s 5.5 ma cki = 4 mhz v cc = 4v, t c = 2.5 s 2.5 ma cki = 1 mhz v cc = 4v, t c = 10 s 1.4 ma halt current (note 4) v cc = 5.5v, cki = 0 mhz < 58 a v cc = 4v, cki = 0 mhz < 34 a idle current cki = 10 mhz v cc = 5.5v, t c = 1 s 3.5 ma cki = 4 mhz v cc = 5.5v, t c = 2.5 s 2.5 ma cki = 1 mhz v cc = 4v, t c = 10 s 0.7 ma input levels reset logic high 0.8 v cc v logic low 0.2 v cc v cki (external and crystal osc. modes) logic high 0.7 v cc v logic low 0.2 v cc v all other inputs logic high 0.7 v cc v logic low 0.2 v cc v hi-z input leakage v cc = 5.5v, v in =0v ?1 +1 a input pullup current v cc = 5.5v, v in = 0v ?40 ?250 a g and l port input hysteresis 0.35 v cc v cop888fh www.national.com 5
dc electrical characteristics cop98xfh: (continued) 0c t a +70c unless otherwise specified parameter conditions min typ max units output current levels d outputs source v cc = 4v, v oh = 3.3v ?0.4 ma v cc = 2.5v, v oh = 1.8v ?0.2 ma sink v cc = 4v, v ol =1v 10 ma v cc = 2.5v, v ol = 0.4v 2.0 ma all others source (weak pull-up mode) v cc = 4v, v oh = 2.7v ?10 ?100 a v cc = 2.5v, v oh = 1.8v ?2.5 ?33 a source (push-pull mode) v cc = 4v, v oh = 3.3v ?0.4 ma v cc = 2.5v, v oh = 1.8v ?0.2 ma sink (push-pull mode) v cc = 4v, v ol = 0.4v 1.6 ma v cc = 2.5v, v ol = 0.4v 0.7 ma tri-state leakage v cc = 5.5v ?1 +1 a allowable sink/source current per pin d outputs (sink) 15 ma all others 3ma maximum input current t a = 25c 100 ma without latchup (note 5) ram retention voltage, v r 500 ns rise 2 v and fall time (min) input capacitance 7pf load capacitance on d2 1000 pf ac electrical characteristics cop98xfh: 0c t a +70c unless otherwise specified parameter conditions min typ max units instruction cycle time (t c )4v v cc 5.5v 1 dc s crystal resonator or external 2.5v v cc < 4v 2.5 dc s r/c oscillator 4v v cc 5.5v 3 dc s 2.5v v cc < 4v 7.5 dc s cki clock duty cycle (note 6) f = max 45 55 % rise time (note 6) f = 10 mhz ext clock 5 s fall time (note 6) f = 10 mhz ext clock 5 s inputs t setup 4v v cc 5.5v 200 ns 2.5v v cc < 4v 500 ns t hold 4v v cc 5.5v 60 ns 2.5v v cc < 4v 150 ns output propagation delay (note 6) r l = 2.2k, c l = 100 pf t pd1 ,t pd0 so, sk 4v v cc 5.5v 0.7 s 2.5v v cc < 4v 1.75 s all others 4v v cc 5.5v 1 s 2.5v v cc < 4v 2.5 s cop888fh www.national.com 6
ac electrical characteristics cop98xfh: (continued) 0c t a +70c unless otherwise specified parameter conditions min typ max units microwire ? setup time (t uws )20ns microwire hold time (t uwh )56ns microwire output propagation delay (t upd ) 220 ns input pulse width interrupt input high time 1 t c interrupt input low time 1 t c timer input high time 1 t c timer input low time 1 t c reset pulse width 1 s note 2: rate of voltage change must be less than 0.5v/ms. note 3: supply current is measured after running 2000 cycles with a square wave cki input, cko open, inputs at rails and outputs open. note 4: the halt mode will stop cki from oscillating in the rc and the crystal configurations. test conditions: all inputs tied to v cc , l and g ports in the tri-state mode and tied to ground, all outputs low and tied to ground. the clock monitor and the comparator are disabled. note 5: pins g6 and reset are designed with a high voltage input network for factory testing. these pins allow input voltages greater than v cc and the pins will have sink current to v cc when biased at voltages greater than v cc (the pins do not have source current when biased at a voltage below v cc ). the effective resis- tance to v cc is 750 w (typical). these two pins will not latch up. the voltage at the pins must be limited to less than 14v. note 6: the output propagation delay is referenced to the end of the instruction cycle where the output change occurs. ds012602-5 figure 3. microwire/plus timing cop888fh www.national.com 7
cop88xfh absolute maximum ratings (note 7) if military/aerospace specified devices are required, please contact the national semiconductor sales office/ distributors for availability and specifications. supply voltage (v cc )7v voltage at any pin ?0.3v to v cc + 0.3v total current into v cc pin (source) 100 ma total current out of gnd pin (sink) 110 ma storage temperature range ?65c to +140c note 7: absolute maximum ratings indicate limits beyond which damage to the device may occur. dc and ac electrical specifications are not ensured when operating the device at absolute maximum ratings. dc electrical characteristics cop88xfh: ?40c t a +85c unless otherwise specified parameter conditions min typ max units operating voltage 2.5 5.5 v power supply ripple (note 8) peak-to-peak 0.1 v cc v supply current (note 9) cki = 10 mhz v cc = 5.5v, t c = 1 s 12.5 ma cki = 4 mhz v cc = 5.5v, t c = 2.5 s 5.5 ma cki = 4 mhz v cc = 4.0v, t c = 2.5 s 2.5 ma cki = 1 mhz v cc = 4.0v, t c = 10 s 1.4 ma halt current (note 10) v cc = 5.5v, cki = 0 mhz < 510 a v cc = 4.0v, cki = 0 mhz < 36 a idle current cki = 10 mhz v cc = 5.5v, t c = 1 s 3.5 ma cki = 4 mhz v cc = 5.5v, t c = 2.5 s 2.5 ma cki = 1 mhz v cc = 4.0v, t c = 10 s 0.7 ma input levels reset logic high 0.8 v cc v logic low 0.2 v cc v cki (all other inputs) logic high 0.7 v cc v logic low 0.2 v cc v hi-z input leakage v cc = 5.5v, v in =0v ?2 +2 a input pullup current v cc = 5.5v, v in = 0v ?40 ?250 a g and l port input hysteresis (note 12) 0.35 v cc v output current levels d outputs source v cc = 4v, v oh = 3.3v ?0.4 ma v cc = 2.5v, v oh = 1.8v ?0.2 ma sink v cc = 4v, v ol =1v 10 ma v cc = 2.5v, v ol = 0.4v 2.0 ma all others source (weak pull-up mode) v cc = 4v, v oh = 2.7v ?10 ?100 a v cc = 2.5v, v oh = 1.8v ?2.5 ?33 a source (push-pull mode) v cc = 4v, v oh = 3.3v ?0.4 ma v cc = 2.5v, v oh = 1.8v ?0.2 ma sink (push-pull mode) v cc = 4v, v ol = 0.4v 1.6 ma v cc = 2.5v, v ol = 0.4v 0.7 ma tri-state leakage v cc = 5.5v ?2 +2 a allowable sink/source current per pin d outputs (sink) 15 ma all others 3ma cop888fh www.national.com 8
dc electrical characteristics cop88xfh: (continued) ?40c t a +85c unless otherwise specified parameter conditions min typ max units maximum input current room temp 100 ma without latchup (notes 11, 12) ram retention voltage, v r 500 ns rise 2 v and fall time (min) input capacitance (note 12) 7 pf load capacitance on d2 (note 12) 1000 pf ac electrical characteristics cop88xfh: ?40c t a +85c unless otherwise specified parameter conditions min typ max units instruction cycle time (t c ) crystal resonator or external 2.5v v cc 4.0v 2.5 dc s 4.0v v cc 5.5v 1.0 dc s r/c oscillator 2.5v v cc < 4.0v 7.5 dc s 4.0v v cc 5.5v 3.0 dc s cki clock duty cycle (note 12) f = max 45 55 % rise time (note 12) f = 10 mhz ext clock 5 s fall time (note 12) f = 10 mhz ext clock 5 s inputs t setup 4.0v v cc 5.5v 200 ns 2.5v v cc < 4.0v 500 ns t hold 4.0v v cc 5.5v 60 ns 2.5v v cc < 4.0v 150 ns output propagation delay r l = 2.2k, c l = 100 pf t pd1 ,t pd0 so, sk 4.0v v cc 5.5v 0.7 s 2.5v v cc < 4.0v 1.75 s all others 4.0v v cc 5.5v 1 s 2.5v v cc < 4.0v 2.5 s microwire setup time (t uws ) (note 12) v cc 3 4.0v 20 ns microwire hold time (t uwh ) (note 12) v cc 3 4.0v 56 ns microwire output propagation delay (t upd )v cc 3 4.0v 220 ns input pulse width (note 13) interrupt input high time 1 t c interrupt input low time 1 t c timer 1, 2, 3 input high time 1 t c timer 1, 2, 3 input low time 1 t c reset pulse width 1 s note 8: maximum rate of voltage change must be less than 0.5v/ms. note 9: supply current is measured after running 2000 cycles with a square wave cki input, cko open, inputs at rails and outputs open. note 10: the halt mode will stop cki from oscillating in the rc and the crystal configurations. measurement of i dd halt is done with device neither sourcing or sinking current; with l, c, and g0g5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to v cc ; clock monitor and comparators disabled. parameter refers to halt mode entered via setting bit 7 of the g port data register. part will pull up cki during halt in crys- tal clock mode. note 11: pins g6 and reset are designed with a high voltage input network. these pins allow input voltages greater than v cc and the pins will have sink current to v cc when biased at voltages greater than v cc (the pins do not have source current when biased at a voltage below v cc ). the effective resistance to v cc is 750 w (typical). these two pins will not latch up. the voltage at the pins must be limited to less than 14v. warning: voltages in excess of 14v will cause damage to the pins. this warning excludes esd transients. note 12: parameter characterized but not tested. note 13: t c = instruction cycle time. cop888fh www.national.com 9
cop68xfh absolute maximum ratings (note 14) if military/aerospace specified devices are required, please contact the national semiconductor sales office/ distributors for availability and specifications. supply voltage (v cc )7v voltage at any pin ?0.3v to v cc + 0.3v total current into v cc pin (source) 100 ma total current out of gnd pin (sink) 110 ma storage temperature range ?65c to +140c note 14: note: absolute maximum ratings indicate limits beyond which dam- age to the device may occur. dc and ac electrical specifications are not en- sured when operating the device at absolute maximum ratings. dc electrical characteristics cop68xfh: ?55c t a +125c unless otherwise specified parameter conditions min typ max units operating voltage 4.5 5.5 v power supply ripple (note 15) peak-to-peak 0.1 v cc v supply current (note 16) cki = 10 mhz v cc = 5.5v, t c = 1 s 12.5 ma cki = 4 mhz v cc = 5.5v, t c = 2.5 s 5.5 ma halt current (note 17) v cc = 5.5v, cki = 0 mhz < 10 30 a idle current cki = 10 mhz v cc = 5.5v, t c = 1 s 3.5 ma cki = 4 mhz v cc = 5.5v, t c = 2.5 s 2.5 ma input levels reset logic high 0.8 v cc v logic low 0.2 v cc v cki (all other inputs) logic high 0.7 v cc v logic low 0.2 v cc v hi-z input leakage v cc = 5.5v, v in =0v ?5 +5 a input pullup current v cc = 5.5v, v in = 0v ?35 ?400 a g and l port input hysteresis (note 19) 0.35 v cc v output current levels d outputs source v cc = 4.5v, v oh = 3.3v ?0.4 ma sink v cc = 4.5v, v ol =1v 9 ma all others source (weak pull-up mode) v cc = 4.5v, v oh = 2.7v ?9 ?140 a source (push-pull mode) v cc = 4.5v, v oh = 3.3v ?0.4 ma sink (push-pull mode) v cc = 4.5v, v ol = 0.4v 1.4 ma tri-state leakage v cc = 5.5v ?5 +5 a allowable sink/source current per pin d outputs (sink) 12 ma all others 2.5 ma maximum input current room temp 100 ma without latchup (notes 18, 19) ram retention voltage, v r 500 ns rise 2 v and fall time (min) input capacitance (note 19) 7 pf load capacitance on d2 (note 19) 1000 pf cop888fh www.national.com 10
ac electrical characteristics cop68xfh: ?55c t a +125c unless otherwise specified parameter conditions min typ max units instruction cycle time (t c ) crystal resonator or external v cc 3 4.5v 1.0 dc s cki clock duty cycle (note 19) f = max 45 55 % rise time (note 19) f = 10 mhz ext clock 5 s fall time (note 19) f = 10 mhz ext clock 5 s inputs t setup v cc 3 4.5v 200 ns t hold v cc 3 4.5v 60 ns output propagation delay (note 20) r l = 2.2k, c l = 100 pf t pd1 ,t pd0 so, sk v cc 3 4.5v 0.7 s all others v cc 3 4.5v 1 s microwire setup time (t uws ) (note 19) 20 ns microwire hold time (t uwh ) (note 19) 56 ns microwire output propagation delay (t upd ) 220 ns input pulse width (note 20) interrupt input high time 1 t c interrupt input low time 1 t c timer 1, 2, 3 input high time 1 t c timer 1, 2, 3 input low time 1 t c reset pulse width 1 s note 15: maximum rate of voltage change must be less than 0.5v/ms. note 16: supply current is measured after running 2000 cycles with a square wave cki input, cko open, inputs at rails and outputs open. note 17: the halt mode will stop cki from oscillating in the rc and the crystal configurations. measurement of i dd halt is done with device neither sourcing or sinking current; with l, c, and g0g5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to v cc ; clock monitor and comparators disabled. parameter refers to halt mode entered via setting bit 7 of the g port data register. part will pull up cki during halt in crys- tal clock mode. note 18: pins g6 and reset are designed with a high voltage input network. these pins allow input voltages greater than v cc and the pins will have sink current to v cc when biased at voltages greater than v cc (the pins do not have source current when biased at a voltage below v cc ). the effective resistance to v cc is 750 w (typical). these two pins will not latch up. the voltage at the pins must be limited to less than 14v. warning: voltages in excess of 14v will cause damage to the pins. this warning excludes esd transients. note 19: parameter characterized but not tested. note 20: t c = instruction cycle time. comparators ac and dc characteristics v cc = 5v, ?40c t a +85c parameter conditions min typ max units input offset voltage 0.4v v in v cc ? 1.5v 10 25 mv input common mode voltage range 0.4 v cc ? 1.5 v low level output current v ol = 0.4v 1.6 ma high level output current v oh = 4.6v 1.6 ma dc supply current per comparator 250 a (when enabled) response time 100 mv 1 s overdrive, 100 pf load cop888fh www.national.com 11
pin descriptions v cc and gnd are the power supply pins. all v cc and gnd pins must be connected. cki is the clock input. this can come from an r/c gener- ated oscillator, or a crystal oscillator (in conjunction with cko). see oscillator description section. reset is the master reset input. see reset description section. the device contains three bidirectional 8-bit i/o ports (c, g and l), where each individual bit may be independently configured as an input (schmitt trigger inputs on ports l and g), output or tri-state under program control. three data memory address locations are allocated for each of these i/o ports. each i/o port has two associated 8-bit memory mapped registers, the configuration register and the output data register. a memory mapped address is also reserved for the input pins of each i/o port. (see the memory map for the various addresses as- sociated with the i/o ports.) figure 4 shows the i/o port configurations. the data and configuration regis- ters allow for each port bit to be individually configured un- der software control as shown below: configura- tion data register port set-up register 0 0 hi-z input (tri-state output) 0 1 input with weak pull-up 1 0 push-pull zero output 1 1 push-pull one output port l is an 8-bit i/o port. all l-pins have schmitt triggers on the inputs. the port l supports multi-input wake up on all eight pins. l1 is used for the usart external clock. l2 and l3 are used for the usart transmit and receive. l4 and l5 are used for the timer input functions t2a and t2b. l6 and l7 are used for the timer input functions t3a and t3b. the port l has the following alternate features: l7 miwu or t3b l6 miwu or t3a l5 miwu or t2b l4 miwu or t2a l3 miwu or rdx l2 miwu or tdx l1 miwu or ckx l0 miwu port g is an 8-bit port with 5 i/o pins (g0, g2g5), an input pin (g6), and two dedicated output pins (g1 and g7). pins g0 and g2g6 all have schmitt triggers on their inputs. pin g1 serves as the dedicated wdout watchdog output, while pin g7 is either input or output depending on the oscil- lator mask option selected. with the crystal oscillator option selected, g7 serves as the dedicated output pin for the cko clock output. with the single-pin r/c oscillator mask option selected, g7 serves as a general purpose input pin but is also used to bring the device out of halt mode with a low to high transition on g7. there are two registers associated with the g port, a data register and a configuration register. therefore, each of the 5 i/o bits (g0, g2g5) can be indi- vidually configured under software control. since g6 is an input only pin and g7 is the dedicated cko clock output pin (crystal clock option) or general purpose in- put (r/c clock option), the associated bits in the data and configuration registers for g6 and g7 are used for special purpose functions as outlined below. reading the g6 and g7 data bits will return zeros. note that the chip will be placed in the halt mode by writing a a1o to bit 7 of the port g data register. similarly the chip will be placed in the idle mode by writing a a1o to bit 6 of the port g data register. writing a a1o to bit 6 of the port g configuration register en- ables the microwire/plus to operate with the alternate phase of the sk clock. the g7 configuration bit, if set high, enables the clock start up delay after halt when the r/c clock configuration is used. config reg. data reg. g7 clkdly halt g6 alternate sk idle port g has the following alternate features: g6 si (microwire serial data input) g5 sk (microwire serial clock) g4 so (microwire serial data output) g3 t1a (timer t1 i/o) g2 t1b (timer t1 capture input) g0 intr (external interrupt input) port g has the following dedicated functions: g7 cko oscillator dedicated output or general purpose input g1 wdout watchdog and/or clock monitor dedi- cated output port c is an 8-bit i/o port. the 40-pin device does not have a full complement of port c pins. the unavailable pins are not terminated. a read operation for these unterminated pins will return unpredicatable values. port i is an eight-bit hi-z input port. the 28-pin device does not have a full complement of port i pins. the unavailable pins are not terminated i.e., they are floating. a read opera- tion for these unterminated pins will return unpredictable val- ues. the user must ensure that the software takes this into account by either masking or restricting the accesses to bit operations. the unterminated port i pins will draw power only when addressed. port i1i3 are used for comparator 1. port i4i6 are used for comparator 2. ds012602-6 figure 4. i/o port configurations cop888fh www.national.com 12
pin descriptions (continued) the port i has the following alternate features. i6 comp2out (comparator 2 output) i5 comp2+in (comparator 2 positive input) i4 comp2?in (comparator 2 negative input) i3 comp1out (comparator 1 output) i2 comp1+in (comparator 1 positive input) i1 comp1?in (comparator 1 negative input) port d is an 8-bit output port that is preset high when reset goes low. the user can tie two or more d port outputs (ex- cept d2) together in order to get a higher drive. note: care must be exercised with the d2 pin operation. at reset, the ex- ternal loads on this pin must ensure that the output voltages stay above 0.8 v cc to prevent the chip from entering special modes. also keep the external loading on d2 to less than 1000 pf. functional description the architecture of the device is modified harvard architec- ture. with the harvard architecture, the control store pro- gram memory (rom) is separated from the data store memory (ram). both rom and ram have their own sepa- rate addressing space with separate address buses. the ar- chitecture, though based on harvard architecture, permits transfer of data from rom to ram. cpu registers the cpu can do an 8-bit addition, subtraction, logical or shift operation in one instruction (t c ) cycle time. there are six cpu registers: a is the 8-bit accumulator register pc is the 15-bit program counter register pu is the upper 7 bits of the program counter (pc) pl is the lower 8 bits of the program counter (pc) b is an 8-bit ram address pointer, which can be optionally post auto incremented or decremented. x is an 8-bit alternate ram address pointer, which can be optionally post auto incremented or decremented. sp is the 8-bit stack pointer, which points to the subroutine/ interrupt stack (in ram). the sp is initialized to ram ad- dress 06f with reset. s is the 8-bit data segment address register used to extend the lower half of the address range (00 to 7f) into 256 data segments of 128 bytes each. all the cpu registers are memory mapped with the excep- tion of the accumulator (a) and the program counter (pc). program memory the program memory consists of 12288 bytes of rom. these bytes may hold program instructions or constant data (data tables for the laid instruction, jump vectors for the jid instruction, and interrupt vectors for the vis instruction). the program memory is addressed by the 15-bit program counter (pc). all interrupts in the devices vector to program memory location 0ff hex. data memory the data memory address space includes the on-chip ram and data registers, the i/o registers (configuration, data and pin), the control registers, the microwire/plus sio shift register, and the various registers, and counters associated with the timers (with the exception of the idle timer). data memory is addressed directly by the instruction or indirectly by the b, x, sp pointers and s register. the data memory consists of 512 bytes of ram. sixteen bytes of ram are mapped as aregisterso at addresses 0f0 to 0ff hex. these registers can be loaded immediately, and also decremented and tested with the drsz (decrement register and skip if zero) instruction. the memory pointer registers x, sp, b and s are memory mapped into this space at address locations 0fc to 0ff hex respectively, with the other registers being available for general usage. the instruction set permits any bit in memory to be set, reset or tested. all i/o and registers (except a and pc) are memory mapped; therefore, i/o bits and register bits can be directly and individually set, reset and tested. the accumula- tor (a) bits can also be directly and individually tested. note: ram contents are undefined upon power-up. data memory segment ram extension data memory address 0ff is used as a memory mapped lo- cation for the data segment address register (s). the data store memory is either addressed directly by a single byte address within the instruction, or indirectly rela- tive to the reference of the b, x, or sp pointers (each con- tains a single-byte address). this single-byte address allows an addressing range of 256 locations from 00 to ff hex. the upper bit of this single-byte address divides the data store memory into two separate sections as outlined previously. with the exception of the ram register memory from ad- dress locations 00f0 to 00ff, all ram memory is memory mapped with the upper bit of the single-byte address being equal to zero. this allows the upper bit of the single-byte ad- dress to determine whether or not the base address range (from 0000 to 00ff) is extended. if this upper bit equals one (representing address range 0080 to 00ff), then address extension does not take place. alternatively, if this upper bit equals zero, then the data segment extension register s is used to extend the base address range (from 0000 to 007f) from xx00 to xx7f, where xx represents the 8 bits from the s register. thus the 128-byte data segment extensions are located from addresses 0100 to 017f for data segment 1, 0200 to 027f for data segment 2, etc., up to ff00 to ff7f for data segment 255. the base address range from 0000 to 007f represents data segment 0. figure 5 illustrates how the s register data memory exten- sion is used in extending the lower half of the base address range (00 to 7f hex) into 256 data segments of 128 bytes each, with a total addressing range of 32 kbytes from xx00 to xx7f. this organization allows a total of 256 data seg- ments of 128 bytes each with an additional upper base seg- ment of 128 bytes. furthermore, all addressing modes are available for all data segments. the s register must be changed under program control to move from one data seg- ment (128 bytes) to another. however, the upper base seg- ment (containing the 16 memory registers, i/o registers, control registers, etc.) is always available regardless of the contents of the s register, since the upper base segment (address range 0080 to 00ff) is independent of data seg- ment extension. the instructions that utilize the stack pointer (sp) always ref- erence the stack as part of the base segment (segment 0), regardless of the contents of the s register. the s register is not changed by these instructions. consequently, the stack (used with subroutine linkage and interrupts) is always lo- cop888fh www.national.com 13
data memory segment ram extension (continued) cated in the base segment. the stack pointer will be intitial- ized to point at data memory location 006f as a result of re- set. the 128 bytes of ram contained in the base segment are split between the lower and upper base segments. the first 112 bytes of ram are resident from address 0000 to 006f in the lower base segment, while the remaining 16 bytes of ram represent the 16 data memory registers located at ad- dresses 00f0 to 00ff of the upper base segment. no ram is located at the upper sixteen addresses (0070 to 007f) of the lower base segment. additional ram beyond these initial 128 bytes, however, will always be memory mapped in groups of 128 bytes (or less) at the data segment address extensions (xx00 to xx7f) of the lower base segment. the additional 128 bytes of ram are memory mapped at address locations 0100 to 017f hex. reset the reset input when pulled low initializes the microcon- troller. initialization will occur whenever the reset input is pulled low. upon initialization, the data and configuration registers for ports l, g and c are cleared, resulting in these ports being initialized to the tri-state mode. pin g1 of the g port is an exception (as noted below) since pin g1 is dedi- cated as the watchdog and/or clock monitor error output pin. port d is set high. the pc, psw, icntrl, cntrl, t2cntrl and t3cntrl control registers are cleared. the usart registers psr, enu (except that tbmt bit is set), enur and enui are cleared. the comparator select regis- ter is cleared. the s register is initialized to zero. the multi-input wakeup registers wken, wkedg and wkpnd are cleared. (wakeup register wkpnd is unknown.) the stack pointer, sp, is initialized to 6f hex. the device comes out of reset with both the watchdog logic and the clock monitor detector armed, with the watchdog service window bits set and the clock monitor bit set. the watchdog and clock monitor circuits are in- hibited during reset. the watchdog service window bits being initialized high default to the maximum watchdog service window of 64k t c clock cycles. the clock monitor bit being initialized high will cause a clock monitor error follow- ing reset if the clock has not reached the minimum specified frequency at the termination of reset. a clock monitor error will cause an active low error output on pin g1. this error output will continue until 16 t c 32 t c clock cycles following the clock frequency reaching the minimum specified value, at which time the g1 output will enter the tri-state mode. the external rc network shown in figure 6 should be used to ensure that the reset pin is held low until the power sup- ply to the chip stabilizes. oscillator circuits the chip can be driven by a clock input on the cki input pin which can be between dc and 10 mhz. the cko output clock is on pin g7 (crystal configuration). the cki input fre- quency is divided down by 10 to produce the instruction cycle clock (t c ). figure 7 shows the crystal and r/c oscillator diagrams. crystal oscillator cki and cko can be connected to make a closed loop crys- tal (or resonator) controlled oscillator. ds012602-7 *reads as all ones. figure 5. ram organization ds012602-8 rc > 5 x power supply rise time figure 6. recommended reset circuit cop888fh www.national.com 14
oscillator circuits (continued) table 1 shows the component values required for various standard crystal values. r/c oscillator by selecting cki as a single pin oscillator input, a single pin r/c oscillator circuit can be connected to it. cko is available as a general purpose input, and/or halt restart input. table 2 shows the variation in the oscillator frequencies as functions of the component (r and c) values. external oscillator cki can be driven by an external clock signal. cko is avail- able as a general purpose input and/or halt restart control. table 1. crystal oscillator configuration, t a = 25c r1 r2 c1 c2 cki freq conditions (k w )(m w ) (pf) (pf) (mhz) 0 1 30 3036 10 v cc =5v 0 1 30 3036 4 v cc =5v 0 1 200 100150 0.455 v cc =5v table 2. rc oscillator configuration, t a = 25c r c cki freq instr. cycle conditions (k w ) (pf) (mhz) (s) 3.3 82 2.2 to 2.7 3.7 to 4.6 v cc =5v 5.6 100 1.1 to 1.3 7.4 to 9.0 v cc =5v 6.8 100 0.9 to 1.1 8.8 to 10.8 v cc =5v note: 3k r 200k 50 pf c 200 pf control registers cntrl register (address x?00ee) t1c3 t1c2 t1c1 t1c0 msel iedg sl1 sl0 bit 7 bit 0 the timer1 (t1) and microwire/plus control register contains the following bits: t1c3 timer t1 mode control bit t1c2 timer t1 mode control bit t1c1 timer t1 mode control bit t1c0 timer t1 start/stop control in timer modes 1 and 2, t1 underflow interrupt pending flag in timer mode 3 msel selects g5 and g4 as microwire/plus signals sk and so respectively iedg external interrupt edge polarity select (0 = rising edge, 1 = falling edge) sl1 & sl0 select the microwire/plus clock divide by (00 = 2, 01 = 4, 1x = 8) psw register (address x?00ef) hc c t1pnda t1ena expnd busy exen gie bit 7 bit 0 the psw register contains the following select bits: hc half carry flag c carry flag t1pnda timer t1 interrupt pending flag (autoreload ra in mode 1, t1 underflow in mode 2, t1a capture edge in mode 3) t1ena timer t1 interrupt enable for timer underflow or t1a input capture edge expnd external interrupt pending busy microwire/plus busy shifting flag exen enable external interrupt gie global interrupt enable (enables interrupts) the half-carry flag is also affected by all the instructions that affect the carry flag. the sc (set carry) and r/c (reset carry) instructions will respectively set or clear both the carry flags. in addition to the sc and r/c instructions, adc, subc, rrc and rlc instructions affect the carry and half carry flags. icntrl register (address x?00e8) reserved lpen t0pnd t0en wpnd wen t1pndb t1enb bit 7 bit 0 the icntrl register contains the following bits: reserved this bit is reserved and must be zero. crystal oscillator ds012602-9 external oscillator ds012602-10 r/c oscillator ds012602-11 figure 7. crystal r/c, and external oscillator diagrams cop888fh www.national.com 15
control registers (continued) lpen l port interrupt enable (multi-input wakeup/ interrupt) t0pnd timer t0 interrupt pending t0en timer t0 interrupt enable (bit 12 toggle) wpnd microwire/plus interrupt pending wen enable microwire/plus interrupt t1pndb timer t1 interrupt pending flag for t1b cap- ture edge t1enb timer t1 interrupt enable for t1b input cap- ture edge t2cntrl register (address x?00c6) t2c3 t2c2 t2c1 t2c0 t2pnda t2ena t2pndb t2enb bit 7 bit 0 the t2cntrl control register contains the following bits: t2c3 timer t2 mode control bit t2c2 timer t2 mode control bit t2c1 timer t2 mode control bit t2c0 timer t2 start/stop control in timer modes 1 and 2, t2 underflow interrupt pend- ing flag in timer mode 3 t2pnda timer t2 interrupt pending flag (autoreload ra in mode 1, t2 underflow in mode 2, t2a capture edge in mode 3) t2ena timer t2 interrupt enable for timer underflow or t2a input capture edge t2pndb timer t2 interrupt pending flag for t2b cap- ture edge t2enb timer t2 interrupt enable for timer underflow or t2b input capture edge t3cntrl register (address x?00b6) t3c3 t3c2 t3c1 t3c0 t3pnda t3ena t3pndb t3enb bit 7 bit 0 the t3cntrl control register contains the following bits: t3c3 timer t3 mode control bit t3c2 timer t3 mode control bit t3c1 timer t3 mode control bit t3c0 timer t3 start/stop control in timer modes 1 and 2, t3 underflow interrupt pend- ing flag in timer mode 3 t3pnda timer t3 interrupt pending flag (autoreload ra in mode 1, t3 underflow in mode 2, t3a capture edge in mode 3) t3ena timer t3 interrupt enable for timer underflow or t3a input capture edge t3pndb timer t3 interrupt pending flag for t3b cap- ture edge t3enb timer t3 interrupt enable for timer underflow or t3b input capture edge timers the device contains a very versatile set of timers (t0, t1, t2, t3). all timers and associated autoreload/capture regis- ters power up containing random data. timer t0 (idle timer) the device supports applications that require maintaining real time and low power with the idle mode. this idle mode support is furnished by the idle timer t0, which is a 16-bit timer. the timer t0 runs continuously at the fixed rate of the instruction cycle clock, t c . the user cannot read or write to the idle timer t0, which is a count down timer. the timer t0 supports the following functions: exit out of the idle mode (see idle mode description) watchdog logic (see watchdog description) start up delay out of the halt mode the idle timer t0 can generate an interrupt when the thir- teenth bit toggles. this toggle is latched into the t0pnd pending flag, and will occur every 4 ms at the maximum clock frequency (t c = 1 s). a control flag t0en allows the in- terrupt from the thirteenth bit of timer t0 to be enabled or disabled. setting t0en will enable the interrupt, while reset- ting it will disable the interrupt. timer t1, timer t2 and timer t3 the device has a set of three powerful timer/counter blocks, t1, t2 and t3. the associated features and functioning of a timer block are described by referring to the timer block tx. since the three timer blocks, t1, t2 and t3 are identical, all comments are equally applicable to any of the three timer blocks. each timer block consists of a 16-bit timer, tx, and two sup- porting 16-bit autoreload/capture registers, rxa and rxb. each timer block has two pins associated with it, txa and txb. the pin txa supports i/o required by the timer block, while the pin txb is an input to the timer block. the powerful and flexible timer block allows the device to easily perform all timer functions with minimal software overhead. the timer block has three operating modes: processor independent pwm mode, external event counter mode, and input cap- ture mode. the control bits txc3, txc2, and txc1 allow selection of the different modes of operation. mode 1. processor independent pwm mode as the name suggests, this mode allows the device to gen- erate a pwm signal with very minimal user intervention. the user only has to define the parameters of the pwm signal (on time and off time). once begun, the timer block will continuously generate the pwm signal completely indepen- dent of the microcontroller. the user software services the timer block only when the pwm parameters require updat- ing. in this mode the timer tx counts down at a fixed rate of t c . upon every underflow the timer is alternately reloaded with the contents of supporting registers, rxa and rxb. the very first underflow of the timer causes the timer to reload from the register rxa. subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the register rxb. the tx timer control bits, txc3, txc2 and txc1 set up the timer for pwm mode operation. figure 8 shows a block diagram of the timer in pwm mode. the underflows can be programmed to toggle the txa output pin. the underflows can also be programmed to generate in- terrupts. underflows from the timer are alternately latched into two pending flags, txpnda and txpndb. the user must reset these pending flags under software control. two control en- cop888fh www.national.com 16
timers (continued) able flags, txena and txenb, allow the interrupts from the timer underflow to be enabled or disabled. setting the timer- enable flag txena will cause an interrupt when a timer un- derflow causes the rxa register to be reloaded into the timer. setting the timer enable flag txenb will cause an interrupt when a timer underflow causes the rxb register to be re- loaded into the timer. resetting the timer enable flags will disable the associated interrupts. either or both of the timer underflow interrupts may be en- abled. this gives the user the flexibility of interrupting once per pwm period on either the rising or falling edge of the pwm output. alternatively, the user may choose to interrupt on both edges of the pwm output. mode 2. external event counter mode this mode is quite similar to the processor independent pwm mode described above. the main difference is that the timer, tx, is clocked by the input signal from the txa pin. the tx timer control bits, txc3, txc2 and txc1 allow the timer to be clocked either on a positive or negative edge from the txa pin. underflows from the timer are latched into the txp- nda pending flag. setting the txena control flag will cause an interrupt when the timer underflows. in this mode the input pin txb can be used as an indepen- dent positive edge sensitive interrupt input if the txenb con- trol flag is set. the occurrence of a positive edge on the txb input pin is latched into the txpndb flag. figure 9 shows a block diagram of the timer in external event counter mode. note: the pwm output is not available in this mode since the txa pin is being used as the counter input clock. mode 3. input capture mode the device can precisely measure external frequencies or time external events by placing the timer block, tx, in the in- put capture mode. in this mode, the timer tx is constantly running at the fixed t c rate. the two registers, rxa and rxb, act as capture regis- ters. each register acts in conjunction with a pin. the register rxa acts in conjunction with the txa pin and the register rxb acts in conjunction with the txb pin. the timer value gets copied over into the register when a trigger event occurs on its corresponding pin. control bits, txc3, txc2 and txc1, allow the trigger events to be speci- fied either as a positive or a negative edge. the trigger con- dition for each input pin can be specified independently. the trigger conditions can also be programmed to generate interrupts. the occurrence of the specified trigger condition on the txa and txb pins will be respectively latched into the pending flags, txpnda and txpndb. the control flag tx- ena allows the interrupt on txa to be either enabled or dis- abled. setting the txena flag enables interrupts to be gener- ated when the selected trigger condition occurs on the txa pin. similarly, the flag txenb controls the interrupts from the txb pin. underflows from the timer can also be programmed to gen- erate interrupts. underflows are latched into the timer txc0 pending flag (the txc0 control bit serves as the timer under- flow interrupt pending flag in the input capture mode). con- sequently, the txc0 control bit should be reset when enter- ing the input capture mode. the timer underflow interrupt is enabled with the txena control flag. when a txa interrupt occurs in the input capture mode, the user must check both the txpnda and txc0 pending flags in order to determine whether a txa input capture or a timer underflow (or both) caused the interrupt. figure 10 shows a block diagram of the timer in input cap- ture mode. ds012602-12 figure 8. timer in pwm mode ds012602-13 figure 9. timer in external event counter mode cop888fh www.national.com 17
timers (continued) timer control flags the control bits and their functions are summarized below. txc3 timer mode control txc2 timer mode control txc1 timer mode control txc0 timer start/stop control in modes 1 and 2 (pro- cessor independent pwm and external event counter), wher e 1 = start , 0 = stop timer underflow interrupt pending flag in mode 3 (input capture) txpnda timer interrupt pending flag txena timer interrupt enable flag 1 = timer interrupt enabled 0 = timer interrupt disabled txpndb timer interrupt pending flag txenb timer interrupt enable flag 1 = timer interrupt enabled 0 = timer interrupt disabled the timer mode control bits (txc3, txc2 and txc1) are detailed below: mode txc3 txc2 txc1 description interrupt a source interrupt b source timer counts on 1 1 0 1 pwm: txa toggle autoreload ra autoreload rb t c 1 0 0 pwm: no txa toggle autoreload ra autoreload rb t c 2 0 0 0 external event counter timer underflow pos. txb edge pos. txa edge 0 0 1 external event counter timer underflow pos. txb edge pos. txa edge 3 0 1 0 captures: pos. txa edge pos. txb edge t c txa pos. edge or timer txb pos. edge underflow 1 1 0 captures: pos. txa neg. txb t c txa pos. edge edge or timer edge txb neg. edge underflow 0 1 1 captures: neg. txa neg. txb t c txa neg. edge edge or timer edge txb neg. edge underflow 1 1 1 captures: neg. txa neg. txb t c txa neg. edge edge or timer edge txb neg. edge underflow power save modes the device offers the user two power save modes of opera- tion: halt and idle. in the halt mode, all microcontroller activities are stopped. in the idle mode, the on-board oscil- lator circuitry and timer t0 are active but all other microcon- troller activities are stopped. in either mode, all on-board ram, registers, i/o states, and timers (with the exception of t0) are unaltered. halt mode the device can be placed in the halt mode by writing a a1o to the halt flag (g7 data bit). all microcontroller activities, including the clock and timers, are stopped. the watch- dog logic on the device is disabled during the halt mode. however, the clock monitor circuitry if enabled remains ac- tive and will cause the watchdog output pin (wdout) to go low. if the halt mode is used and the user does not want to activate the wdout pin, the clock monitor should be dis- abled after the device comes out of reset (resetting the clock monitor control bit with the first write to the wdsvr register). in the halt mode, the power requirements of the device are minimal and the applied voltage (v cc ) may be decreased to v r (v r = 2.0v) without altering the state of the machine. the device supports three different ways of exiting the halt mode. the first method of exiting the halt mode is with the multi-input wakeup feature on the l port. the second method is with a low to high transition on the cko (g7) pin. this method precludes the use of the crystal clock configura- ds012602-14 figure 10. timer in input capture mode cop888fh www.national.com 18
power save modes (continued) tion (since cko becomes a dedicated output), and so may be used with an rc clock configuration. the third method of exiting the halt mode is by pulling the reset pin low. since a crystal or ceramic resonator may be selected as the oscillator, the wakeup signal is not allowed to start the chip running immediately since crystal oscillators and ceramic resonators have a delayed start up time to reach full ampli- tude and frequency stability. the idle timer is used to gen- erate a fixed delay to ensure that the oscillator has indeed stabilized before allowing instruction execution. in this case, upon detecting a valid wakeup signal, only the oscillator cir- cuitry is enabled. the idle timer is loaded with a value of 256 and is clocked with the t c instruction cycle clock. the t c clock is derived by dividing the oscillator clock down by a fac- tor of 10. the schmitt trigger following the cki inverter on the chip ensures that the idle timer is clocked only when the oscillator has a sufficiently large amplitude to meet the schmitt trigger specifications. this schmitt trigger is not part of the oscillator closed loop. the startup timeout from the idle timer enables the clock signals to be routed to the rest of the chip. if an rc clock option is being used, the fixed delay is intro- duced optionally. a control bit, clkdly, mapped as configu- ration bit g7, controls whether the delay is to be introduced or not. the delay is included if clkdly is set, and excluded if clkdly is reset. the clkdly bit is cleared on reset. the device has two mask options associated with the halt mode. the first mask option enables the halt mode feature, while the second mask option disables the halt mode. with the halt mode enable mask option, the device will enter and exit the halt mode as described above. with the halt disable mask option, the device cannot be placed in the halt mode (writing a a1o to the halt flag will have no effect, the halt flag will remain a0o). idle mode the device is placed in the idle mode by writing a a1o to the idle flag (g6 data bit). in this mode, all activities, except the associated on-board oscillator circuitry, and the idle timer t0, are stopped. the power supply requirements of the microcontroller in this mode of operation are typically around 30% of normal power requirement of the microcontroller. as with the halt mode, the device can be returned to nor- mal operation with a reset, or with a multi-input wakeup from the l port. alternately, the microcontroller resumes normal operation from the idle mode when the thirteenth bit (repre- senting 4.096 ms at internal clock frequency of 1 mhz, t c = 1 s) of the idle timer toggles. this toggle condition of the thirteenth bit of the idle timer t0 is latched into the t0pnd pending flag. the user has the option of being interrupted with a transition on the thirteenth bit of the idle timer t0. the interrupt can be enabled or disabled via the t0en control bit. setting the t0en flag enables the interrupt and vice versa. the user can enter the idle mode with the timer t0 inter- rupt enabled. in this case, when the t0pnd bit gets set, the device will first execute the timer t0 interrupt service routine and then return to the instruction following the aenter idle modeo instruction. alternatively, the user can enter the idle mode with the idle timer t0 interrupt disabled. in this case, the device will resume normal operation with the instruction immediately following the aenter idle modeo instruction. note: it is necessary to program two nop instructions following both the set halt mode and set idle mode instructions. these nop instructions are necessary to allow clock resynchronization following the halt or idle modes. multi-input wakeup the multi-input wakeup feature is ued to return (wakeup) the device from either the halt or idle modes. alternately multi-input wakeup/interrupt feature may also be used to generate up to 8 edge selectable external interrupts. figure 11 shows the multi-input wakeup logic. cop888fh www.national.com 19
multi-input wakeup (continued) the multi-input wakeup feature utilizes the l port. the user selects which particular l port bit (or combination of l port bits) will cause the device to exit the halt or idle modes. the selection is done through the reg: wken. the reg: wken is an 8-bit read/write register, which contains a con- trol bit for every l port bit. setting a particular wken bit en- ables a wakeup from the associated l port pin. the user can select whether the trigger condition on the se- lected l port pin is going to be either a positive edge (low to high transition) or a negative edge (high to low transition). this selection is made via the reg: wkedg, which is an 8-bit control register with a bit assigned to each l port pin. setting the control bit will select the trigger condition to be a negative edge on that particular l port pin. resetting the bit selects the trigger condition to be a positive edge. changing an edge select entails several steps in order to avoid a pseudo wakeup condition as a result of the edge change. first, the associated wken bit should be reset, followed by the edge select change in wkedg. next, the associated wkpnd bit should be cleared, followed by the associated wken bit being re-enabled. an example may serve to clarify this procedure. suppose we wish to change the edge select from positive (low going high) to negative (high going low) for l port bit 5, where bit 5 has previously been enabled for an input interrupt. the program would be as follows: rbit 5, wken ; disable miwn sbit 5, wkedg ; change edge polarity rbit 5, wkpnd ; reset pending flag sbit 5, wken ; enable miwu if the l port bits have been used as outputs and then changed to inputs with multi-input wakeup/interrupt, a safety procedure should also be followed to avoid inherited pseudo wakeup conditions. after the selected l port bits have been changed from output to input but before the associated wken bits are enabled, the associated edge select bits in wkedg should be set or reset for the desired edge selects, followed by the associated wkpnd bits being cleared. this same procedure should be used following reset, since the l port inputs are left floating as a result of reset. the occurrence of the selected trigger condition for multi-input wakeup is latched into a pending register called wkpnd. the respective bits of the wkpnd register will be- set on the occurrence of the selected trigger edge on the cor- responding port l pin. the user has the responsibility of clearing these pending flags. since wkpnd is a pending register for the occurrence of selected wakeup conditions, the device will not enter the halt mode if any wakeup bit is both enabled and pending. consequently, the user has the responsibility of clearing the pending flags before attempting to enter the halt mode. wken, wkpnd and wkedg are all read/write registers, and are cleared at reset. port l interrupts port l provides the user with an additional eight fully select- able, edge sensitive interrupts which are all vectored into the same service subroutine. the interrupt from port l shares logic with the wake up cir- cuitry. the register wken allows interrupts from port l to be individually enabled or disabled. the register wkedg speci- fies the trigger condition to be either a positive or a negative edge. finally, the register wkpnd latches in the pending trigger conditions. the gie (global interrupt enable) bit enables the interrupt function. a control flag, lpen, functions as a global interrupt enable for port l interrupts. setting the lpen flag will enable inter- ds012602-15 0 = low going high - 1 = high going low figure 11. multi-input wake up logic cop888fh www.national.com 20
multi-input wakeup (continued) rupts and vice versa. a separate global pending flag is not needed since the register wkpnd is adequate. since port l is also used for waking the device out of the halt or idle modes, the user can elect to exit the halt or idle modes either with or without the interrupt enabled. if he elects to disable the interrupt, then the device will restart ex- ecution from the instruction immediately following the in- struction that placed the microcontroller in the halt or idle modes. in the other case, the device will first execute the in- terrupt service routine and then revert to normal operation. (see halt mode for clock option wakeup information.) note: there is always the possibility of an interrupt occurring during an in- struction which is attempting to reset the gie bit or any other interrupt enable bit. if this occurs when a single cycle instruction is being used to reset the interrupt enable bit, the interrupt enable bit will be reset but an interrupt may still occur. this is because interrupt processing is started at the same time as the interrupt bit is being reset. to avoid this scenario, the user should always use a two, three, or four cycle instruc- tion to reset interrupt enable bits. usart the device contains a full-duplex software programmable usart. the usart ( figure 12 ) consists of a transmit shift register, a receiver shift register and seven addressable reg- isters, as follows: a transmit buffer register (tbuf), a re- ceiver buffer register (rbuf), a usart control and status register (enu), a usart receive control and status register (enur), a usart interrupt and clock source register (enui), a prescaler select register (psr) and baud (baud) register. the enu register contains flags for transmit and re- ceive functions; this register also determines the length of the data frame (7, 8 or 9 bits), the value of the ninth bit in transmission, and parity selection bits. the enur register flags framming, data overrun and parity errors while the us- art is receiving. other functions of the enur register include saving the ninth bit received in the data frame, enabling or disabling the usart's attention mode of operation and providing addi- tional receiver/transmitter status information via rcvg and xmtg bits. the determination of an internal or external clock source is done by the enui register, as well as selecting the number of stop bits and enabling or disabling transmit and receive interrupts. a control flag in this register can also se- lect the usart mode of operation: asynchronous or synchronous. ds012602-16 figure 12. usart block diagram cop888fh www.national.com 21
usart (continued) usart control and status registers the operation of the usart is programmed through three registers: enu, enur and enui. description of usart register bits enu-usart control and status register (address at 0ba) pen psel1 xbit9/ chl1 chl0 err rbfl tbmt psel0 bit 7 bit 0 pen: this bit enables/disables parity (7- and 8-bit modes only). read/write, cleared on reset. pen = 0 parity disabled. pen = 1 parity enabled. psel1, psel0: parity select bits. read/write, cleared on reset. psel1 = 0, psel0 = 0 odd parity (if parity enabled) psel1 = 0, psel0 = 1 even parity (if parity enabled) psel1 = 1, psel0 = 0 mark(1) (if parity enabled) psel1 = 1, psel0 = 1 space(0) (if parity enabled) xbit9/psel0: programs the ninth bit for transmission when the usart is operating with nine data bits per frame. for seven or eight data bits per frame, this bit in conjunction with psel1 selects parity. read/write, cleared on reset. chl1, chl0: these bits select the character frame format. parity is not included and is generated/verified by hardware. read/write, cleared on reset. chl1 = 0, chl0 = 0 the frame contains eight data bits. chl1 = 0, chl0 = 1 the frame contains seven data bits. chl1 = 1, chl0 = 0 the frame contains nine data bits. chl1 = 1, chl0 = 1 loopback mode selected. trans- mitter output internally looped back to receiver input. nine bit framing format is used. err: this bit is a global usart error flag which gets set if any or a combination of the errors (doe, fe, pe) occur. read only; it cannot be written by software, cleared on reset. rbfl: this bit is set when the usart has received a com- plete character and has copied it into the rbuf register. it is automatically reset when software reads the character from rbuf. read only; it cannot be written by software, cleared on reset. tbmt: this bit is set when the usart transfers a byte of data from the tbuf register into the tsft register for trans- mission. it is automatically reset when software writes into the tbuf register. read only, bit is set to aoneo on reset; it cannot be written by software. enur-usart receive control and status register (address at 0bb) doe fe pe reserved rbit9 attn xmtg rcvg (note 21) bit 7 bit 0 note 21: bit is reserved for future use. user must set to zero. doe: flags a data overrun error. read only, cleared on read, cleared on reset. doe = 0 indicates no data overrun error has been de- tected since the last time the enur register was read. doe = 1 indicates the occurrence of a data overrun er- ror. fe: flags a framing error. read only, cleared on read, cleared on reset. fe = 0 indicates no framing error has been detected since the last time the enur register was read. fe = 1 indicates the occurrence of a framing error. pe: flags a parity error. read only, cleared on read, cleared on reset. pe = 0 indicates no parity error has been detected since the last time the enur register was read. pe = 1 indicates the occurrence of a parity error. spare: reserved for future use. read/write, cleared on re- set. rbit9: contains the ninth data bit received when the us- art is operating with nine data bits per frame. read only, cleared on reset. attn: attention mode is enabled while this bit is set. this bit is cleared automatically on receiving a character with data bit nine set. read/write, cleared on reset. xmtg: this bit is set to indicate that the usart is transmit- ting. it gets reset at the end of the last frame (end of last stop bit). read only, cleared on reset. rcvg: this bit is set high whenever a framing error occurs and goes low when rdx goes high. read only, cleared on reset. enui-usart interrupt and clock source register (address at 0bc) stp2 stp78 etdx ssel xrclk xtclk eri eti bit 7 bit 0 stp2: this bit programs the number of stop bits to be trans- mitted. read/write, cleared on reset. stp2 = 0 one stop bit transmitted. stp2 = 1 two stop bits transmitted. stp78: this bit is set to program the last stop bit to be 7/8th of a bit in length. read/write, cleared on reset. etdx: tdx (usart transmit pin) is the alternate function assigned to port l pin l2; it is selected by setting etdx bit. to simulate line break generation, software should reset etdx bit and output logic zero to tdx pin through port l data and configuration registers. read/write, cleared on re- set. ssel: usart mode select. read/write, cleared on reset. ssel = 0 asynchronous mode. ssel = 1 synchronous mode. xrclk: this bit selects the clock source for the receiver section. read/write, cleared on reset. xrclk = 0 the clock source is selected through the psr and baud registers. xrclk = 1 signal on ckx (l1) pin is used as the clock. xtclk: this bit selects the clock source for the transmitter section. read/write, cleared on reset. xtclk = 0 the clock source is selected through the psr and baud registers. xtclk = 1 signal on ckx (l1) pin is used as the clock. eri: this bit enables/disables interrupt from the receiver section. read/write, cleared on reset. eri = 0 interrupt from the receiver is disabled. eri = 1 interrupt from the receiver is enabled. cop888fh www.national.com 22
usart (continued) eti: this bit enables/disables interrupt from the transmitter section. read/write, cleared on reset. eti = 0 interrupt from the transmitter is disabled. eti = 1 interrupt from the transmitter is enabled. associated i/o pins data is transmitted on the tdx pin and received on the rdx pin. tdx is the alternate function assigned to port l pin l2; it is selected by setting etdx (in the enui register) to one. rdx is an inherent function of port l pin l3, requiring no setup. the baud rate clock for the usart can be generated on-chip, or can be taken from an external source. port l pin l1 (ckx) is the external clock i/o pin. the ckx pin can be either an input or an output, as determined by port l con- figuration and data registers (bit 1). as an input, it accepts a clock signal which may be selected to drive the transmitter and/or receiver. as an output, it presents the internal baud rate generator output. usart operation the usart has two modes of operation: asynchronous mode and synchronous mode. asynchronous mode this mode is selected by resetting the ssel (in the enui register) bit to zero. the input frequency to the usart is 16 times the baud rate. the tsft and tbuf registers double-buffer data for trans- mission. while tsft is shifting out the current character on the tdx pin, the tbuf register may be loaded by software with the next byte to be transmitted. when tsft finishes transmitting the current character the contents of tbuf are transferred to the tsft register and the transmit buffer empty flag (tbmt in the enu register) is set. the tbmt flag is automatically reset by the usart when software loads a new character into the tbuf register. there is also the xmtg bit which is set to indicate that the usart is transmitting. this bit gets reset at the end of the last frame (end of last stop bit). tbuf is a read/write register. the rsft and rbuf registers double-buffer data being re- ceived. the usart receiver continually monitors the signal on the rdx pin for a low level to detect the beginning of a start bit. upon sensing this low level, it waits for half a bit time and samples again. if the rdx pin is still low, the re- ceiver considers this to be a valid start bit, and the remaining bits in the character frame are each sampled a single time, at the mid-bit position. serial data input on the rdx pin is shifted into the rsft register. upon receiving the complete character, the contents of the rsft register are copied into the rbuf register and the received buffer full flag (rbfl) is set. rbfl is automatically reset when software reads the character from the rbuf register. rbuf is a read only reg- ister. there is also the rcvg bit which is set high when a framing error occurs and goes low once rdx goes high. tbmt, xmtg, rbfl and rcvg are read only bits. synchronous mode in this mode data is transferred synchronously with the clock. data is transmitted on the rising edge and received on the falling edge of the synchronous clock. this mode is selected by setting ssel bit in the enui regis- ter. the input frequency to the usart is the same as the baud rate. when an external clock input is selected at the ckx pin, data transmit and receive are performed synchronously with this clock through tdx/rdx pins. if data transmit and receive are selected with the ckx pin as clock output, the device generates the synchronous clock output at the ckx pin. the internal baud rate generator is used to produce the synchronous clock. data transmit and receive are performed synchronously with this clock. framing formats the usart supports several serial framing formats ( figure 13 ). the format is selected using control bits in the enu, enur and enui registers. the first format (1, 1a, 1b, 1c) for data transmission (chl0 = 1, chl1 = 0) consists of start bit, seven data bits (excluding parity) and 7/8, one or two stop bits. in applications using parity, the parity bit is generated and verified by hardware. the second format (chl0 = 0, chl1 = 0) consists of one start bit, eight data bits (excluding parity) and 7/8, one or two stop bits. parity bit is generated and verified by hard- ware. the third format for transmission (chl0 = 0, chl1 = 1) con- sists of one start bit, nine data bits and 7/8, one or two stop bits. this format also supports the usart aattentiono feature. when operating in this format, all eight bits of tbuf and rbuf are used for data. the ninth data bit is transmitted and received using two bits in the enu and enur registers, called xbit9 and rbit9. rbit9 is a read only bit. parity is not generated or verified in this mode. for any of the above framing formats, the last stop bit can be programmed to be 7/8th of a bit in length. if two stop bits are selected and the 7/8th bit is set (selected), the second stop bit will be 7/8th of a bit in length. the parity is enabled/disabled by pen bit located in the enu register. parity is selected for 7- and 8-bit modes only. if par- ity is enabled (pen = 1), the parity selection is then per- formed by psel0 and psel1 bits located in the enu regis- ter. note that the xbit9/psel0 bit located in the enu register serves two mutually exclusive functions. this bit programs the ninth bit for transmission when the usart is operating with nine data bits per frame. there is no parity selection in this framing format. for other framing formats xbit9 is not needed and the bit is psel0 used in conjunction with psel1 to select parity. the frame formats for the receiver differ from the transmitter in the number of stop bits required. the receiver only re- quires one stop bit in a frame, regardless of the setting of the stop bit selection bits in the control register. note that an im- plicit assumption is made for full duplex usart operation that the framing formats are the same for the transmitter and receiver. cop888fh www.national.com 23
usart operation (continued) usart interrupts the usart is capable of generating interrupts. interrupts are generated on receive buffer full and transmit buffer empty. both interrupts have individual interrupt vectors. two bytes of program memory space are reserved for each inter- rupt vector. the two vectors are located at addresses 0xec to 0xef hex in the program memory space. the interrupts can be individually enabled or disabled using enable trans- mit interrupt (eti) and enable receive interrupt (eri) bits in the enui register. the interrupt from the transmitter is set pending, and re- mains pending, as long as both the tbmt and eti bits are set. to remove this interrupt, software must either clear the eti bit or write to the tbuf register (thus clearing the tbmt bit). the interrupt from the receiver is set pending, and remains pending, as long as both the rbfl and eri bits are set. to remove this interrupt, software must either clear the eri bit or read from the rbuf register (thus clearing the rbfl bit). baud clock generation the clock inputs to the transmitter and receiver sections of the usart can be individually selected to come either from an external source at the ckx pin (port l, pin l1) or from a source selected in the psr and baud registers. internally, the basic baud clock is created from the oscillator frequency through a two-stage divider chain consisting of a 116 (in- crements of 0.5) prescaler and an 11-bit binary counter. ( fig- ure 14 ) the divide factors are specified through two read/ write registers shown in figure 15 . note that the 11-bit baud rate divisor spills over into the prescaler select register (psr). psr is cleared upon reset. as shown in table 3 , a prescaler factor of 0 corresponds to no clock. no clock condition is the usart power down mode where the usart clock is turned off for power saving purpose. the user must also turn the usart clock off when a different baud rate is chosen. the correspondences between the 5-bit prescaler select and prescaler factors are shown in table 3 . there are many ways to calculate the two divisor factors, but one particularly effective method would be to achieve a 1.8432 mhz fre- quency coming out of the first stage. the 1.8432 mhz pres- caler output is then used to drive the software programmable baud rate counter to create a 16x clock for the following baud rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400, 3600, 4800, 7200, 9600, 19200 and 38400 table 4 . other baud rates may be created by using appropriate divisors. the 16x clock is then divided by 16 to provide the rate for the serial shift registers of the transmitter and receiver. ds012602-17 figure 13. framing formats cop888fh www.national.com 24
baud clock generation (continued) table 3. prescaler factors prescaler prescaler select factor 00000 no clock 00001 1 00010 1.5 00011 2 00100 2.5 00101 3 00110 3.5 00111 4 01000 4.5 01001 5 01010 5.5 01011 6 01100 6.5 01101 7 01110 7.5 01111 8 10000 8.5 10001 9 10010 9.5 10011 10 10100 10.5 10101 11 10110 11.5 10111 12 11000 12.5 11001 13 11010 13.5 11011 14 11100 14.5 11101 15 prescaler prescaler select factor 11110 15.5 11111 16 table 4. baud rate divisors (1.8432 mhz prescaler output) baud baud rate rate diviso r ? 1 (n-1) 110 (110.03) 1046 134.5 (134.58) 855 150 767 300 383 600 191 1200 95 1800 63 2400 47 3600 31 4800 23 7200 15 9600 11 19200 5 38400 2 the entries in table 4 assume a prescaler output of 1.8432 mhz. in the asynchronous mode the baud rate could be as high as 625k. as an example, considering the asynchronous mode and a cki clock of 4.608 mhz, the prescaler factor selected is: 4.608/1.8432 = 2.5 the 2.5 entry is available in table 3 . the 1.8432 mhz pres- caler output is then used with proper baud rate divisor table 4 to obtain different baud rates. for a baud rate of 19200 e.g., the entry in table 4 is 5. n?1=5(n?1isthe value from table 4 ) n = 6 (n is the baud rate divisor) baud rate = 1.8432 mhz/(16 x 6) = 19200 ds012602-18 figure 14. usart baud clock generation ds012602-19 figure 15. usart baud clock divisor registers cop888fh www.national.com 25
baud clock generation (continued) the divide by 16 is performed because in the asynchronous mode, the input frequency to the usart is 16 times the baud rate. the equation to calculate baud rates is given be- low. the actual baud rate may be found from: br = fc/(1 6xnxp) where: br is the baud rate fc is the cki frequency n is the baud rate divisor ( table 4 ). p is the prescaler divide factor selected by the value in the prescaler select register ( table 3 ) note: in the synchronous mode, the divisor 16 is replaced by two. example: asynchronous mode: crystal frequency = 5 mhz desired baud rate = 9600 using the above equatio nnxpcanbe calculated first. nxp=(5x10 6 )/(16 x 9600) = 32.552 now 32.552 is divided by each prescaler factor ( table 4 )to obtain a value closest to an integer. this factor happens to be 6.5 (p = 6.5). n = 32.552/6.5 = 5.008 (n = 5) the programmed value (from table 4 ) should be 4 (n ? 1). using the above values calculated for n and p: br=(5x10 6 )/(1 6x5x 6.5) = 9615.384 % error = (9615.385 ? 9600)/9600 = 0.16 effect of halt/idle the usart logic is reinitialized when either the halt or idle modes are entered. this reinitialization sets the tbmt flag and resets all read only bits in the usart control and status registers. read/write bits remain unchanged. the transmit buffer (tbuf) is not affected, but the transmit shift register (tsft) bits are set to one. the receiver registers rbuf and rsft are not affected. the device will exit from the halt/idle modes when the start bit of a character is detected at the rdx (l3) pin. this feature is obtained by using the multi-input wakeup scheme provided on the device. before entering the halt or idle modes the user program must select the wakeup source to be on the rdx pin. this selection is done by setting bit 3 of wken (wakeup enable) register. the wakeup trigger condition is then selected to be high to low transition. this is done via the wkedg register (bit 3 is one.) if the device is halted and crystal oscillator is used, the wakeup signal will not start the chip running immediately be- cause of the finite start up time requirement of the crystal os- cillator. the idle timer (t0) generates a fixed (256 t c ) delay to ensure that the oscillator has indeed stabilized before allow- ing the device to execute code. the user has to consider this delay when data transfer is expected immediately after exit- ing the halt mode. diagnostic bits chl0 and chl1 in the enu register provide a loopback feature for diagnostic testing of the usart. when these bits are set to one, the following occur: the receiver input pin (rdx) is internally connected to the transmitter output pin (tdx); the output of the transmitter shift register is alooped backo into the receive shift register input. in this mode, data that is transmitted is immediately received. this feature allows the processor to verify the transmit and receive data paths of the usart. note that the framing format for this mode is the nine bit for- mat; one start bit, nine data bits, and 7/8, one or two stop bits. parity is not generated or verified in this mode. attention mode the usart receiver section supports an alternate mode of operation, referred to as attention mode. this mode of operation is selected by the attn bit in the enur register. the data format for transmission must also be selected as having nine data bits and either 7/8, one or two stop bits. the attention mode of operation is intended for use in networking the device with other processors. typically in such environments the messages consists of device ad- dresses, indicating which of several destinations should re- ceive them, and the actual data. this mode supports a scheme in which addresses are flagged by having the ninth bit of the data field set to a 1. if the ninth bit is reset to a zero the byte is a data byte. while in attention mode, the usart monitors the com- munication flow, but ignores all characters until an address character is received. upon receiving an address character, the usart signals that the character is ready by setting the rbfl flag, which in turn interrupts the processor if usart receiver interrupts are enabled. the attn bit is also cleared automatically at this point, so that data characters as well as address characters are recognized. software examines the contents of the rbuf and responds by deciding either to ac- cept the subsequent data stream (by leaving the attn bit re- set) or to wait until the next address character is seen (by setting the attn bit again). operation of the usart transmitter is not affected by selec- tion of this mode. the value of the ninth bit to be transmitted is programmed by setting xbit9 appropriately. the value of the ninth bit received is obtained by reading rbit9. since this bit is located in enur register where the error flags re- side, a bit operation on it will reset the error flags. comparators the device contains two differential comparators, each with a pair of inputs (positive and negative) and an output. ports i1i3 and i4i6 are used for the comparators. the following is the port i assignment: i6 comparator2 output i5 comparator2 positive input i4 comparator2 negative input i3 comparator1 output i2 comparator1 positive input i1 comparator1 negative input a comparator select register (cmpsl) is used to enable the comparators, read the outputs of the comparators inter- nally, and enable the outputs of the comparators to the pins. two control bits (enable and output enable) and one result bit are associated with each comparator. the comparator re- sult bits (cmp1rd and cmp2rd) are read only bits which will read as zero if the associated comparator is not enabled. the comparator select register is cleared with reset, result- ing in the comparators being disabled. the comparators cop888fh www.national.com 26
comparators (continued) should also be disabled before entering either the halt or idle modes in order to save power. the configuration of the cmpsl register is as follows: cmpsl register (address x'00b7) rsvd cmp20e cmp2rd cmp2en cmp10e cmp1rd cmp1en rsvd bit 7 bit 0 the cmpsl register contains the following bits: rsvd these bit are reserved and must be zero cmp20e selects pin i6 as comparator 2 output provided that cmp2en is set to enable the comparator cmp2rd comparator 2 result (this is a read only bit, which will read as 0 if the comparator is not enabled) cmp2en enable comparator 2 cmp10e selects pin i3 as comparator 1 output provided that cmpien is set to enable the comparator cmp1rd comparator 1 result (this is a read only bit, which will read as 0 if the comparator is not enabled) cmp1en enable comparator 1 note that the two unused bits of cmpsl may be used as software flags. comparator outputs have the same spec as ports l and g except that the rise and fall times are symmetrical. multiply/divide this device contains a multiply/divide block. this block sup- port s a 1 byte x 2 bytes (3 bytes result) multiply or a 3 bytes/2 bytes (2 bytes result) divide operation. the multiply or divide operation is executed by setting control bits located in the multiply/divide control register. the multiply or divide operands must be placed into the appropriate memory mapped locations before the operation is initiated. control register bits rsvd rsvd rsvd rsvd rsvd div div mult ovf bit 7 bit 0 the multiply/divide control register (mdcr) is located at ad- dress xx9d. it has the following bit assignments: rsvd these bits are reserved and must be zero divovf division overflow (if the result of a division is greater than 16 bits or the user attempted to divide by zero; 1 = error) div start division operation (1 = start) mult start multiplication operation (1 = start) after the appropriate mdr registers are loaded, the mult and div start bits are set by the user to start a multiply or di- vide operation. the division operation has priority, if both bits are set simultaneously. the mult and div bits are both automatically cleared by hardware at the end of a divide or multiply operation. each division operation causes the divovf flag to be set/reset as appropriate. the divovf flag is cleared following a multiplication operation. divovf is a read-only bit. the mult and div bits are read/writable. bits 37 in mdcr should not be used, as the mult and div operations will change their values. multiply/divide operation for the multiply operation, the multiplicand is placed at ad- dresses xx9b and xx9c. the multiplier is placed at address xx99. for the divide operation, the dividend is placed at ad- dresses xx98 to xx9a and the divisor is placed at addresses xx9b to xx9c. in both operations, all operands are inter- preted as unsigned values. the divide or multiply operation is started by setting the appropriate mdcr bit. if both the mult and div bits are set, the microcontroller performs a di- vide operation. (the user is not required to read or clear the divovf error bit prior to beginning a new multiply/divide op- eration. this bit is ignored during subsequent operations. however, the next divide operation will overwrite the error flag as appropriate, and the next multiply operation will clear it.) the multiply operation requires 1 instruction cycle to com- plete. the divide operation requires 2 instruction cycles to complete. a divide by zero or a division which produces an overflow requires only 1 instruction cycle to execute. the mdr1 through mdr5 registers and the mdcr register can not be read from or written to during a multiply or divide op- eration. any attempt to write in to these registers will be ig- nored. any attempt to read these registers will return unde- fined data. the result of a multiply is placed in addresses xx99xx9b. the result of a divide is placed in a ddresses xx98xx99. if a division by zero is attempted or if the resulting quotient of a divide operation is more than 16 bits long, then the divovf bit is set in the multiply/divide control register. the dividend and the divisor are left unchanged. the divide operation al- ways causes the divovf flag to be set or reset as appropri- ate. the divovf flag is cleared following a multiply opera- tion. reset state a reset signal applied to the device during normal operation has the following affects: mdcr is cleared, and any operation in progress is stopped. mdr1 through mdr5 are undefined. cop888fh www.national.com 27
multiply/divide (continued) table 5. multiply/divide registers register name (address) multiplication assignment division assignment before operation after operation before operation after operation mdr1 (xx98) unused unchanged low byte of dividend low byte of result mdr2 (xx99) multiplier low byte of result middle byte of dividend high byte of result mdr3 (xx9a) middle byte of result high byte of dividend undefined mdr4 (xx9b) low byte of multiplicand high byte of result low byte of divisor low byte of divisor mdr5 (xx9c) high byte of multiplicand unchanged high byte of divisor high byte of divisor interrupts introduction each device supports thirteen vectored interrupts. interrupt sources include timer 0, timer 1, timer 2, timer 3, port l wakeup, software trap, microwire/plus, and external input. all interrupts force a branch to location 00ff hex in program memory. the vis instruction may be used to vector to the appropriate service routine from location 00ff hex. the software trap has the highest priority while the default vis has the lowest priority. each of the 13 maskable inputs has a fixed arbitration rank- ing and vector. figure 16 shows the interrupt block diagram. ds012602-20 figure 16. interrupt block diagram cop888fh www.national.com 28
interrupts (continued) maskable interrupts all interrupts other than the software trap are maskable. each maskable interrupt has an associated enable bit and pending flag bit. the pending bit is set to 1 when the interrupt condition occurs. the state of the interrupt enable bit, com- bined with the gie bit determines whether an active pending flag actually triggers an interrupt. all of the maskable inter- rupt pending and enable bits are contained in mapped con- trol registers, and thus can be controlled by the software. a maskable interrupt condition triggers an interrupt under the following conditions: 1. the enable bit associated with that interrupt is set. 2. the gie bit is set. 3. the device is not processing a non-maskable interrupt. (if a non-maskable interrupt is being serviced, a maskable interrupt must wait until that service routine is completed.) an interrupt is triggered only when all of these conditions are met at the beginning of an instruction. if different maskable interrupts meet these conditions simultaneously, the highest priority interrupt will be serviced first, and the other pending interrupts must wait. upon reset, all pending bits, individual enable bits, and the gie bit are reset to zero. thus, a maskable interrupt condi- tion cannot trigger an interrupt until the program enables it by setting both the gie bit and the individual enable bit. when enabling an interrupt, the user should consider whether or not a previously activated (set) pending bit should be ac- knowledged. if, at the time an interrupt is enabled, any pre- vious occurrences of the interrupt should be ignored, the as- sociated pending bit must be reset to zero prior to enabling the interrupt. otherwise, the interrupt may be simply en- abled; if the pending bit is already set, it will immediately trig- ger an interrupt. a maskable interrupt is active if its associ- ated enable and pending bits are set. an interrupt is an asychronous event which may occur be- fore, during, or after an instruction cycle. any interrupt which occurs during the execution of an instruction is not acknowl- edged until the start of the next normally executed instruction is to be skipped, the skip is performed before the pending in- terrupt is acknowledged. at the start of interrupt acknowledgment, the following ac- tions occur: 1. the gie bit is automatically reset to zero, preventing any subsequent maskable interrupt from interrupting the cur- rent service routine. this feature prevents one maskable interrupt from interrupting another one being serviced. 2. the address of the instruction about to be executed is pushed onto the stack. 3. the program counter (pc) is loaded with 00ff hex, causing a jump to that program memory location. the device requires seven instruction cycles to perform the actions listed above. if the user wishes to allow nested interrupts, the interrupts service routine may set the gie bit to 1 by writing to the psw register, and thus allow other maskable interrupts to interrupt the current service routine. if nested interrupts are allowed, caution must be exercised. the user must write the program in such a way as to prevent stack overflow, loss of saved context information, and other unwanted conditions. the interrupt service routine stored at location 00ff hex should use the vis instruction to determine the cause of the interrupt, and jump to the interrupt handling routine corre- sponding to the highest priority enabled and active interrupt. alternately, the user may choose to poll all interrupt pending and enable bits to determine the source(s) of the interrupt. if more than one interrupt is active, the user's program must decide which interrupt to service. within a specific interrupt service routine, the associated pending bit should be cleared. this is typically done as early as possible in the service routine in order to avoid missing the next occurrence of the same type of interrupt event. thus, if the same event occurs a second time, even while the first occurrence is still being serviced, the second occur- rence will be serviced immediately upon return from the cur- rent interrupt routine. an interrupt service routine typically ends with an reti in- struction. this instruction sets the gie bit back to 1, pops the address stored on the stack, and restores that address to the program counter. program execution then proceeds with the next instruction that would have been executed had there been no interrupt. if there are any valid interrupts pending, the highest-priority interrupt is serviced immediately upon re- turn from the previous interrupt. vis instruction the general interrupt service routine, which starts at address 00ff hex, must be capable of handling all types of inter- rupts. the vis instruction, together with an interrupt vector table, directs the device to the specific interrupt handling rou- tine based on the cause of the interrupt. vis is a single-byte instruction, typically used at the very be- ginning of the general interrupt service routine at address 00ff hex, or shortly after that point, just after the code used for context switching. the vis instruction determines which enabled and pending interrupt has the highest priority, and causes an indirect jump to the address corresponding to that interrupt source. the jump addresses (vectors) for all pos- sible interrupts sources are stored in a vector table. the vector table may be as long as 32 bytes (maximum of 16 vectors) and resides at the top of the 256-byte block contain- ing the vis instruction. however, if the vis instruction is at the very top of a 256-byte block (such as at 00ff hex), the vector table resides at the top of the next 256-byte block. thus, if the vis instruction is located somewhere between 00ff and 01df hex (the usual case), the vector table is lo- cated between addresses 01e0 and 01ff hex. if the vis in- struction is located between 01ff and 02df hex, then the vector table is located between addresses 02e0 and 02ff hex, and so on. each vector is 15 bits long and points to the beginning of a specific interrupt service routine somewhere in the 32 kbyte memory space. each vector occupies two bytes of the vector table, with the higher-order byte at the lower address. the vectors are arranged in order of interrupt priority. the vector of the maskable interrupt with the lowest rank is located to 0ye0 (higher-order byte) and 0ye1 (lower-order byte). the next priority interrupt is located at 0ye2 and 0ye3, and so forth in increasing rank. the software trap has the highest rank and its vector is always located at 0yfe and 0yff. the number of interrupts which can become active defines the size of the table. table 6 shows the types of interrupts, the interrupt arbitration ranking, and the locations of the corresponding vectors in the vector table. the vector table should be filled by the user with the memory locations of the specific interrupt service routines. for ex- cop888fh www.national.com 29
interrupts (continued) ample, if the software trap routine is located at 0310 hex, then the vector location 0yfe and -0yff should contain the data 03 and 10 hex, respectively. when a software trap in- terrupt occurs and the vis instruction is executed, the pro- gram jumps to the address specified in the vector table. the interrupt sources in the vector table are listed in order of rank, from highest to lowest priority. if two or more enabled and pending interrupts are detected at the same time, the one with the highest priority is serviced first. upon return from the interrupt service routine, the next highest-level pending interrupt is serviced. if the vis instruction is executed, but no interrupts are en- abled and pending, the lowest-priority interrupt vector is used, and a jump is made to the corresponding address in the vector table. this is an unusual occurrence, and may be the result of an error. it can legitimately result from a change in the enable bits or pending flags prior to the execution of the vis instruction, such as executing a single cycle instruc- tion which clears an enable flag at the same time that the pending flag is set. it can also result, however, from inadvert- ent execution of the vis command outside of the context of an interrupt. the default vis interrupt vector can be useful for applica- tions in which time critical interrupts can occur during the servicing of another interrupt. rather than restoring the pro- gram context (a, b, x, etc.) and executing the reti instruc- tion, an interrupt service routine can be terminated by return- ing to the vis instruction. in this case, interrupts will be serviced in turn until no further interrupts are pending and the default vis routine is started. after testing the gie bit to ensure that execution is not erroneous, the routine should restore the program context and execute the reti to return to the interrupted program. this technique can save up to fifty instruction cycles (t c ), or more, (50s at 10 mhz oscillator) of latency for pending in- terrupts with a penalty of fewer than ten instruction cycles if no further interrupts are pending. to ensure reliable operation, the user should always use the vis instruction to determine the source of an interrupt. al- though it is possible to poll the pending bits to detect the source of an interrupt, this practice is not recommended. the use of polling allows the standard arbitration ranking to be al- tered, but the reliability of the interrupt system is compro- mised. the polling routine must individually test the enable and pending bits of each maskable interrupt. if a software trap interrupt should occur, it will be serviced last, even though it should have the highest priority. under certain con- ditions, a software trap could be triggered but not serviced, resulting in an inadvertent alocking outo of all maskable inter- rupts by the software trap pending flag. problems such as this can be avoided by using vis instruction. table 6. interrupt vector table arbitration vector ranking source description address hi-low byte (1) highest software intr instruction 0yfe0yff (2) reserved 0yfc0yfd (3) external pin g0 edge 0yfa0yfb (4) timer t0 underflow 0yf80yf9 (5) timer t1 t1a/underflow 0yf60yf7 (6) timer t1 t1b 0yf40yf5 (7) microwire/plus busy goes low 0yf20yf3 (8) reserved 0yf00yf1 (9) uart receive 0yee0yef (10) uart transmit 0yec0yed (11) timer t2 t2a/underflow 0yea0yeb (12) timer t2 t2b 0ye80ye9 (13) timer t3 t3a/underflow 0ye60ye7 (14) timer t3 t3b 0ye40ye5 (15) port l/wakeup port l edge 0ye20ye3 (16) lowest default vis reserved 0ye00ye1 note 22: y is a variable which represents the vis block. vis and the vector table must be located in the same 256-byte block except if vis is located at the last ad- dress of a block. in this case, the table must be in the next block. vis execution when the vis instruction is executed it activates the arbitra- tion logic. the arbitration logic generates an even number between e0 and fe (e0, e2, e4, e6 etc...) depending on which active interrupt has the highest arbitration ranking at the time of the 1st cycle of vis is executed. for example, if the software trap interrupt is active, fe is generated. if the external interrupt is active and the software trap interrupt is not, then fa is generated and so forth. if the only active inter- rupt is software trap, than e0 is generated. this number re- places the lower byte of the pc. the upper byte of the pc re- mains unchanged. the new pc is therefore pointing to the vector of the active interrupt with the highest arbitration rank- ing. this vector is read from program memory and placed into the pc which is now pointed to the 1st instruction of the service routine of the active interrupt with the highest arbitra- tion ranking. cop888fh www.national.com 30
interrupts (continued) figure 17 illustrates the different steps performed by the vis instruction. figure 18 shows a flowchart for the vis instruc- tion. the non-maskable interrupt pending flag is cleared by the rpnd (reset non-maskable pending bit) instruction (under certain conditions) and upon reset. ds012602-26 figure 17. vis operation ds012602-27 figure 18. vis flowchart cop888fh www.national.com 31
interrupts (continued) programming example: external interrupt psw =00ef cntrl =00ee rbit 0,portgc rbit 0,portgd ; g0 pin configured hi-z sbit iedg, cntrl ; ext interrupt polarity; falling edge sbit exen, psw ; enable the external interrupt sbit gie, psw ; set the gie bit wait: jp wait ; wait for external interrupt . . . .=0ff ; the interrupt causes a vis ; branch to address 0ff ; the vis causes a branch to ;interrupt vector table . . . .=01fa ; vector table (within 256 byte .addrw service ; of vis inst.) containing the ext ; interrupt service routine . . int_exit: reti . . service: rbit expnd, psw ; interrupt service routine ; reset ext interrupt pend. bit . . . jp int_exit ; return, set the gie bit cop888fh www.national.com 32
interrupts (continued) non-maskable interrupt pending flag there is a pending flag bit associated with the non-maskable interrupt, called stpnd. this pending flag is not memory- mapped and cannot be accessed directly by the software. the pending flag is reset to zero when a device reset oc- curs. when the non-maskable interrupt occurs, the associ- ated pending bit is set to 1. the interrupt service routine should contain an rpnd instruction to reset the pending flag to zero. the rpnd instruction always resets the stpnd flag. software trap the software trap is a special kind of non-maskable inter- rupt which occurs when the intr instruction (used to ac- knowledge interrupts) is fetched from program memory and placed in the instruction register. this can happen in a vari- ety of ways, usually because of an error condition. some ex- amples of causes are listed below. if the program counter incorrectly points to a memory loca- tion beyond the available program memory space, the non- existent or unused memory location returns zeroes which is interpreted as the intr instruction. if the stack is popped beyond the allowed limit (address 06f hex), a 7fff will be loaded into the pc, if this last location in program memory is unprogrammed or unavailable, a soft- ware trap will be triggered. a software trap can be triggered by a temporary hardware condition such as a brownout or power supply glitch. the software trap has the highest priority of all interrupts. when a software trap occurs, the stpnd bit is set. the gie bit is not affected and the pending bit (not accessible by the user) is used to inhibit other interrupts and to direct the pro- gram to the st service routine with the vis instruction. noth- ing can interrupt a software trap service routine except for another software trap. the stpnd can be reset only by the rpnd instruction or a chip reset. the software trap indicates an unusual or unknown error condition. generally, returning to normal execution at the point where the software trap occurred cannot be done re- liably. therefore, the software trap service routine should reinitialize the stack pointer and perform a recovery proce- dure that restarts the software at some known point, similar to a device reset, but not necessarily performing all the same functions as a device reset. the routine must also ex- ecute the rpnd instruction to reset the stpnd flag. other- wise, all other interrupts will be locked out. to the extent pos- sible, the interrupt routine should record or indicate the context of the device so that the cause of the software trap can be determined. if the user wishes to return to normal execution from the point at which the software trap was triggered, the user must first execute rpnd, followed by retsk rather than reti or ret. this is because the return address stored on the stack is the address of the intr instruction that triggered the interrupt. the program must skip that instruction in order to proceed with the next one. otherwise, an infinite loop of software traps and returns will occur. programming a return to normal execution requires careful consideration. if the software trap routine is interrupted by another software trap, the rpnd instruction in the service routine for the second software trap will reset the stpnd flag; upon return to the first software trap routine, the stpnd flag will have the wrong state. this will allow maskable interrupts to be acknowledged during the servicing of the first software trap. to avoid problems such as this, the user program should contain the software trap routine to perform a recovery procedure rather than a return to normal execution. under normal conditions, the stpnd flag is reset by a rpnd instruction in the software trap service routine. if a programming error or hardware condition (brownout, power supply glitch, etc.) sets the stpnd flag without providing a way for it to be cleared, all other interrupts will be locked out. to alleviate this condition, the user can use extra rpnd in- structions in the main program and in the watchdog ser- vice routine (if present). there is no harm in executing extra rpnd instructions in these parts of the program. port l interrupts port l provides the user with an additional eight fully select- able, edge sensitive interrupts which are all vectored into the same service subroutine. the interrupt from port l shares logic with the wake up cir- cuitry. the register wken allows interrupts from port l to be individually enabled or disabled. the register wkedg speci- fies the trigger condition to be either a positive or a negative edge. finally, the register wkpnd latches in the pending trigger conditions. the gie (global interrupt enable) bit enables the interrupt function. a control flag, lpen, functions as a global interrupt enable for port l interrupts. setting the lpen flag will enable inter- rupts and vice versa. a separate global pending flag is not needed since the register wkpnd is adequate. since port l is also used for waking the device out of the halt or idle modes, the user can elect to exit the halt or idle modes either with or without the interrupt enabled. if he elects to disable the interrupt, then the device will restart ex- ecution from the instruction immediately following the in- struction that placed the microcontroller in the halt or idle modes. in the other case, the device will first execute the in- terrupt service routine and then revert to normal operation. (see halt mode for clock option wakeup information.) interrupt summary the device uses the following types of interrupts, listed be- low in order of priority: 1. the software trap non-maskable interrupt, triggered by the intr (00 opcode) instruction. the software trap is acknowledged immediately. this interrupt service rou- tine can be interrupted only by another software trap. the software trap should end with two rpnd instruc- tions followed by a restart procedure. 2. maskable interrupts, triggered by an on-chip peripheral block or an external device connected to the device. un- der ordinary conditions, a maskable interrupt will not in- terrupt any other interrupt routine in progress. a maskable interrupt routine in progress can be inter- rupted by the non-maskable interrupt request. a maskable interrupt routine should end with an reti in- struction or, prior to restoring context, should return to execute the vis instruction. this is particularly useful when exiting long interrupt service routiness if the time between interrupts is short. in this case the reti instruc- tion would only be executed when the default vis rou- tine is reached. cop888fh www.national.com 33
watchdog the device contains a watchdog and clock monitor. the watchdog is designed to detect the user program getting stuck in infinite loops resulting in loss of program control or arunawayo programs. the clock monitor is used to detect the absence of a clock or a very slow clock below a specified rate on the cki pin. the watchdog consists of two independent logic blocks: wd upper and wd lower. wd upper establishes the upper limit on the service window and wd lower defines the lower limit of the service window. servicing the watchdog consists of writing a specific value to a watchdog service register named wdsvr which is memory mapped in the ram. this value is com- posed of three fields, consisting of a 2-bit window select, a 5-bit key data field, and the 1-bit clock monitor select field. table 7 shows the wdsvr register. the lower limit of the service window is fixed at 2048 instruc- tion cycles. bits 7 and 6 of the wdsvr register allow the user to pick an upper limit of the service window. table 8 shows the four possible combinations of lower and upper limits for the watchdog service window. this flex- ibility in choosing the watchdog service window prevents any undue burden on the user software. bits 5, 4, 3, 2 and 1 of the wdsvr register represent the 5-bit key data field. the key data is fixed at 01100. bit 0 of the wdsvr register is the clock monitor select bit. table 7. watchdog service register (wdsvr) window key data clock select monitor xx01100 y 7654321 0 table 8. watchdog service window select wdsvr wdsvr clock service window bit 7 bit 6 monitor (lower-upper limits) 0 0 x 20488k t c cycles 0 1 x 204816k t c cycles 1 0 x 204832k t c cycles 1 1 x 204864k t c cycles x x 0 clock monitor disabled x x 1 clock monitor enabled clock monitor the clock monitor aboard the device can be selected or de- selected under program control. the clock monitor is guar- anteed not to reject the clock if the instruction cycle clock (1/ t c ) is greater or equal to 10 khz. this equates to a clock input rate on cki of greater or equal to 100 khz. watchdog operation the watchdog and clock monitor are disabled during re- set. the device comes out of reset with the watchdog armed, the watchdog window select bits (bits 6, 7 of the wdsvr register) set, and the clock monitor bit (bit 0 of the wdsvr register) enabled. thus, a clock monitor error will occur after coming out of reset, if the instruction cycle clock frequency has not reached a minimum specified value, in- cluding the case where the oscillator fails to start. the wdsvr register can be written to only once after reset and the key data (bits 5 through 1 of the wdsvr register) must match to be a valid write. this write to the wdsvr reg- ister involves two irrevocable choices: (i) the selection of the watchdog service window (ii) enabling or disabling of the clock monitor. hence, the first write to wdsvr register in- volves selecting or deselecting the clock monitor, select the watchdog service window and match the watchdog key data. subsequent writes to the wdsvr register will compare the value being written by the user to the watch- dog service window value and the key data (bits 7 through 1) in the wdsvr register. table 9 shows the sequence of events that can occur. the user must service the watchdog at least once before the upper limit of the service window expires. the watch- dog may not be serviced more than once in every lower limit of the service window. the user may service the watchdog as many times as wished in the time period be- tween the lower and upper limits of the service window. the first write to the wdsvr register is also counted as a watchdog service. the watchdog has an output pin associated with it. this is the wdout pin, on pin 1 of the port g. wdout is active low. the wdout pin is in the high impedance state in the in- active state. upon triggering the watchdog, the logic will pull the wdout (g1) pin low for an additional 16 t c 32t c cycles after the signal level on wdout pin goes below the lower schmitt trigger threshold. after this delay, the device will stop forcing the wdout output low. the watchdog service window will restart when the wd- out pin goes high. it is recommended that the user tie the wdout pin back to v cc through a resistor in order to pull wdout high. a watchdog service while the wdout signal is active will be ignored. the state of the wdout pin is not guaranteed on reset, but if it powers up low then the watchdog will time out and wdout will enter high impedance state. the clock monitor forces the g1 pin low upon detecting a clock frequency error. the clock monitor error will continue until the clock frequency has reached the minimum specified value, after which the g1 output will enter the high imped- ance tri-state mode following 16 t c 32 t c clock cycles. the clock monitor generates a continual clock monitor error if the oscillator fails to start, or fails to reach the minimum specified frequency. the specification for the clock monitor is as follows: 1/t c > 10 khz e no clock rejection. 1/t c < 10 hz e guaranteed clock rejection. watchdog and clock monitor summary the following salient points regarding the watchdog and clock monitor should be noted: both the watchdog and clock monitor detector circuits are inhibited during reset. following reset, the watchdog and clock moni- tor are both enabled, with the watchdog having he maximum service window selected. the watchdog service window and clock moni- tor enable/disable option can only be changed once, during the initial watchdog service following reset. cop888fh www.national.com 34
watchdog operation (continued) the initial watchdog service must match the key data value in the watchdog service register wdsvr in or- der to avoid a watchdog error. subsequent watchdog services must match all three data fields in wdsvr in order to avoid watchdog er- rors. the correct key data value cannot be read from the watchdog service register wdsvr. any attempt to read this key data value of 01100 from wdsvr will read as key data value of all 0's. the watchdog detector circuit is inhibited during both the halt and idle modes. the clock monitor detector circuit is active during both the halt and idle modes. consequently, the de- vice inadvertently entering the halt mode will be de- tected as a clock monitor error (provided that the clock monitor enable option has been selected by the program). with the single-pin r/c oscillator mask option selected and the clkdly bit reset, the watchdog service win- dow will resume following halt mode from where it left off before entering the halt mode. with the crystal oscillator mask option selected, or with the single-pin r/c oscillator mask option selected and the clkdly bit set, the watchdog service window will be set to its selected value from wdsvr following halt. consequently, the watchdog should not be serviced for at least 2048 instruction cycles following halt, but must be serviced within the selected window to avoid a watchdog error. the idle timer t0 is not initialized with reset. the user can sync in to the idle counter cycle with an idle counter (t0) interrupt or by monitoring the t0pnd flag. the t0pnd flag is set whenever the thirteenth bit of the idle counter toggles (every 4096 instruction cycles). the user is responsible for resetting the t0pnd flag. a hardware watchdog service occurs just as the de- vice exits the idle mode. consequently, the watch- dog should not be serviced for at least 2048 instruction cycles following idle, but must be serviced within the se- lected window to avoid a watchdog error. following reset, the initial watchdog service (where the service window and the clock monitor enable/ disable must be selected) may be programmed any- where within the maximum service window (65,536 in- struction cycles) initialized by reset. note that this initial watchdog service may be programmed within the ini- tial 2048 instruction cycles without causing a watch- dog error. detection of illegal conditions the device can detect various illegal conditions resulting from coding errors, transient noise, power supply voltage drops, runaway programs, etc. reading of undefined rom gets zeros. the opcode for soft- ware interrupt is zero. if the program fetches instructions from undefined rom, this will force a software interrupt, thus signaling that an illegal condition has occurred. the subroutine stack grows down for each call (jump to sub- routine), interrupt, or push, and grows up for each return or pop. the stack pointer is initialized to ram location 06f hex during reset. consequently, if there are more returns than calls, the stack pointer will point to addresses 070 and 071 hex (which are undefined ram). undefined ram from ad- dresses 070 to 07f (segment 0), 140 to 17f (segment 1), and all other segments (i.e., segment s 2 ? etc.) is read as all 1's, which in turn will cause the program to return to ad- dress 7fff hex. this is an undefined rom location and the instruction fetched (all 0's) from this location will generate a software interrupt signaling an illegal condition. thus, the chip can detect the following illegal conditions: 1. executing from undefined rom 2. over apopoing the stack by having more returns than calls. when the software interrupt occurs, the user can re-initialize the stack pointer and do a recovery procedure before restart- ing (this recovery program is probably similar to that follow- ing reset, but might not contain the same program initializa- tion procedures). the recovery program should reset the software interrupt pending bit using the rpnd instruction. microwire/plus microwire/plus is a serial synchronous communications interface. the microwire/plus capability enables the de- vice to interface with any of national semiconductor's mi- crowire peripherals (i.e. a/d converters, display drivers, e 2 proms etc.) and with other microcontrollers which sup- port the microwire interface. it consists of an 8-bit serial shift register (sio) with serial data input (si), serial data out- put (so) and serial shift clock (sk). figure 19 shows a block diagram of the microwire/plus logic. the shift clock can be selected from either an internal source or an external source. operating the microwire/plus ar- rangement with the internal clock source is called the master mode of operation. similarly, operating the microwire/ plus arrangement with an external shift clock is called the slave mode of operation. the cntrl register is used to configure and control the microwire/plus mode. to use the microwire/plus, the msel bit in the cntrl register is set to one. in the mas- ter mode, the sk clock rate is selected by the two bits, sl0 and sl1, in the cntrl register. table 10 details the different clock rates that may be selected. ds012602-22 figure 19. microwire/plus block diagram cop888fh www.national.com 35
microwire/plus (continued) table 9. watchdog service actions key window clock action data data monitor match match match valid service: restart service window don't care mismatch don't care error: generate watchdog output mismatch don't care don't care error: generate watchdog output don't care don't care mismatch error: generate watchdog output table 10. microwire/plus master mode clock select sl1 sl0 sk 0 0 2xt c 0 1 4xt c 1 x 8xt c where t c is the instruction cycle clock microwire/plus operation setting the busy bit in the psw register causes the microwire/plus to start shifting the data. it gets reset when eight data bits have been shifted. the user may reset the busy bit by software to allow less than 8 bits to shift. if enabled, an interrupt is generated when eight data bits have been shifted. the device may enter the microwire/plus mode either as a master or as a slave. figure 20 shows how two devices, microcontrollers and several peripherals may be interconnected using the microwire/plus arrange- ments. warning: the sio register should only be loaded when the sk clock is low. loading the sio register while the sk clock is high will result in undefined data in the sio register. sk clock is nor- mally low when not shifting. setting the busy flag when the input sk clock is high in the microwire/plus slave mode may cause the current sk clock for the sio shift register to be narrow. for safety, the busy flag should only be set when the input sk clock is low. microwire/plus master mode operation in the microwire/plus master mode of operation the shift clock (sk) is generated internally by the device. the mi- crowire master always initiates all data exchanges. the msel bit in the cntrl register must be set to enable the so and sk functions onto the g port. the so and sk pins must also be selected as outputs by setting appropriate bits in the port g configuration register. table vii summarizes the bit settings required for master mode of operation. microwire/plus slave mode operation in the microwire/plus slave mode of operation the sk clock is generated by an external source. setting the msel bit in the cntrl register enables the so and sk functions onto the g port. the sk pin must be selected as an input and the so pin is selected as an output pin by setting and re- setting the appropriate bits in the port g configuration regis- ter. table vii summarizes the settings required to enter the slave mode of operation. the user must set the busy flag immediately upon entering the slave mode. this will ensure that all data bits sent by the master will be shifted properly. after eight clock pulses the busy flag will be cleared and the sequence may be re- peated. alternate sk phase operation the device allows either the normal sk clock or an alternate phase sk clock to shift data in and out of the sio register. in both the modes the sk is normally low. in the normal mode data is shifted in on the rising edge of the sk clock and the data is shifted out on the falling edge of the sk clock. the sio register is shifted on each falling edge of the sk clock. in the alternate sk phase operation, data is shifted in on the falling edge of the sk clock and shifted out on the rising edge of the sk clock. a control flag, sksel, allows either the normal sk clock or the alternate sk clock to be selected. resetting sksel causes the microwire/plus logic to be clocked from the normal sk signal. setting the sksel flag selects the alter- nate sk clock. the sksel is mapped into the g6 configura- tion bit. the sksel flag will power up in the reset condition, selecting the normal sk signal. table 11. microwire/plus mode settings this table assumes that the control flag msel is set. g4 (so) g5 (sk) g4 g5 operation config. bit config. bit fun. fun. 1 1 so int. microwire/plus sk master 0 1 tri- int. microwire/plus state sk master 1 0 so ext. microwire/plus sk slave 0 0 tri- ext. microwire/plus state sk slave cop888fh www.national.com 36
microwire/plus (continued) ds012602-23 figure 20. microwire/plus application cop888fh www.national.com 37
memory map all ram, ports and registers (except a and pc) are mapped into data memory address space. address contents s/add reg 0000 to 006f on-chip ram bytes (112 bytes) 0070 to 007f unused ram address space (reads as all ones) xx80 to xx97 unused ram address space (reads undefined data) xx98 dividend or result byte (mdr1) xx99 dividend/multiplier or result byte (mdr2) xx9a dividend/result byte or undefined (mdr3) xx9b dividend/multiplicand or result byte (mdr4) xx9c divisor or multiplicand byte (mdr5) xx9d multiply/divide control register (mdcr) xx9e to xxaf reserved xxb0 timer t3 lower byte xxb1 timer t3 upper byte xxb2 timer t3 autoload register t3ra lower byte xxb3 timer t3 autoload register t3ra upper byte xxb4 timer t3 autoload register t3rb lower byte xxb5 timer t3 autoload register t3rb upper byte xxb6 timer t3 control register xxb7 comparator select register (cmpsl) xxb8 uart transmit buffer (tbuf) xxb9 uart receive buffer (rbuf) xxba uart control and status register (enu) xxbb uart receive control and status register (enur) xxbc uart interrupt and clock source register (enui) xxbd uart baud register (baud) xxbe uart prescale select register (psr) xxbf reserved for uart xxc0 timer t2 lower byte xxc1 timer t2 upper byte xxc2 timer t2 autoload register t2ra lower byte xxc3 timer t2 autoload register t2ra upper byte xxc4 timer t2 autoload register t2rb lower byte xxc5 timer t2 autoload register t2rb upper byte xxc6 timer t2 control register address contents s/add reg xxc7 watchdog service register (reg:wdsvr) xxc8 miwu edge select register (reg:wkedg) xxc9 miwu enable register (reg:wken) xxca miwu pending register (reg:wkpnd) xxcb reserved xxcc reserved xxcd to xxcf reserved xxd0 port l data register xxd1 port l configuration register xxd2 port l input pins (read only) xxd3 reserved for port l xxd4 port g data register xxd5 port g configuration register xxd6 port g input pins (read only) xxd7 port i input pins (read only) xxd8 port c data register xxd9 port c configuration register xxda port c input pins (read only) xxdb reserved for port c xxdc port d xxdd to xxdf reserved for port d xxe0 to xxe5 reserved for ee control registers xxe6 timer t1 autoload register t1rb lower byte xxe7 timer t1 autoload register t1rb upper byte xxe8 icntrl register xxe9 microwire/plus shift register xxea timer t1 lower byte xxeb timer t1 upper byte xxec timer t1 autoload register t1ra lower byte xxed timer t1 autoload register t1ra upper byte xxee cntrl control register xxef psw register xxf0 to xxfb on-chip ram mapped as registers xxfc x register xxfd sp register xxfe b register xxff s register 0100 to 017f on-chip 128 ram bytes 0200 to 027f on-chip 128 ram bytes 0300 to 037f on-chip 128 ram bytes note: reading memory locations 0070h007fh (segment 0) will return all ones. reading unused memory locations 0080h00afh (segment 0) will re- turn undefined data. reading memory locations from other unused segments (i.e., segment 4, segment 5, ? etc.) will return undefined data. cop888fh www.national.com 38
addressing modes there are ten addressing modes, six for operand addressing and four for transfer of control. operand addressing modes register indirect this is the anormalo addressing mode. the operand is the data memory addressed by the b pointer or x pointer. register indirect (with auto post increment or decrement of pointer) this addressing mode is used with the ld and x instruc- tions. the operand is the data memory addressed by the b pointer or x pointer. this is a register indirect mode that au- tomatically post increments or decrements the b or x regis- ter after executing the instruction. direct the instruction contains an 8-bit address field that directly points to the data memory for the operand. immediate the instruction contains an 8-bit immediate field as the oper- and. short immediate this addressing mode is used with the load b immediate in- struction. the instruction contains a 4-bit immediate field as the operand. indirect this addressing mode is used with the laid instruction. the contents of the accumulator are used as a partial address (lower 8 bits of pc) for accessing a data operand from the program memory. transfer of control addressing modes relative this mode is used for the jp instruction, with the instruction field being added to the program counter to get the new pro- gram location. jp has a range from ?31 to +32 to allow a 1-byte relative jump (jp + 1 is implemented by a nop in- struction). there are no apageso when using jp, since all 15 bits of pc are used. absolute this mode is used with the jmp and jsr instructions, with the instruction field of 12 bits replacing the lower 12 bits of the program counter (pc). this allows jumping to any loca- tion in the current 4k program memory segment. absolute long this mode is used with the jmpl and jsrl instructions, with the instruction field of 15 bits replacing the entire 15 bits of the program counter (pc). this allows jumping to any loca- tion up to 32k program memory space. indirect this mode is used with the jid instruction. the contents of the accumulator are used as a partial address (lower 8 bits of pc) for accessing a location in the program memory. the contents of this program memory location serve as a partial address (lower 8 bits of pc) for the jump to the next instruc- tion. note: the vis is a special case of the indirect transfer of control addressing mode, where the double byte vector associated with the interrupt is transferred from adjacent addresses in the program memory into the program counter (pc) in order to jump to the associated interrupt ser- vice routine. instruction set register and symbol definition registers a 8-bit accumulator register b 8-bit address register x 8-bit address register sp 8-bit stack pointer register pc 15-bit program counter register pu upper 7 bits of pc pl lower 8 bits of pc c 1 bit of psw register for carry hc 1 bit of psw register for half carry gie 1 bit of psw register for global interrupt enable vu interrupt vector upper byte vl interrupt vector lower byte symbols [b] memory indirectly addressed by b register [x] memory indirectly addressed by x register md direct addressed memory mem direct addressed memory or [b] meml direct addressed memory or [b] or immediate data imm 8-bit immediate data reg register memory: addresses f0 to ff (includes b, x and sp) bit bit number (0 to 7) ? loaded with ? exchanged with cop888fh www.national.com 39
instruction set (continued) instruction set add a,meml add a ? a + meml adc a,meml add with carry a ? a+meml+c,c ? carry hc ? half carry subc a,meml subtract with carry a ? a?memi+c,c ? carry hc ? half carry and a,meml logical and a ? a and meml andsz a,imm logical and immed., skip if zero skip next if (a and imm) = 0 or a,meml logical or a ? a or meml xor a,meml logical exclusive or a ? a xor meml ifeq md,imm if equal compare md and imm, do next if md = imm ifeq a,meml if equal compare a and meml, do next if a = meml ifne a,meml if not equal compare a and meml, do next if a 1 meml ifgt a,meml if greater than compare a and meml, do next if a > meml ifbne # if b not equal do next if lower 4 bits of b 1 imm drsz reg decrement reg., skip if zero reg ? reg ? 1, skip if reg = 0 sbit # ,mem set bit 1 to bit, mem (bit = 0 to 7 immediate) rbit # ,mem reset bit 0 to bit, mem ifbit # ,mem if bit if bit in a or mem is true do next instruction rpnd reset pending flag reset software interrupt pending flag x a,mem exchange a with memory a ? mem x a,[x] exchange a with memory [x] a ? [x] ld a,meml load a with memory a ? meml ld a,[x] load a with memory [x] a ? [x] ld b,imm load b with immed. b ? imm ld mem,imm load memory immed mem ? imm ld reg,imm load register memory immed. reg ? imm xa,[b ] exchange a with memory [b] a ? [b], (b ? b 1) xa,[x ] exchange a with memory [x] a ? [x], (x ? x 1) ld a, [b ] load a with memory [b] a ? [b], (b ? b 1) ld a, [x ] load a with memory [x] a ? [x], (x ? x 1) ld [b ],imm load memory [b] immed. [b] ? imm, (b ? b 1) clr a clear a a ? 0 inc a increment a a ? a+1 dec a decrementa a ? a?1 laid load a indirect from rom a ? rom (pu,a) dcor a decimal correct a a ? bcd correction of a (follows adc, subc) rrc a rotate a right thru c c ? a7 ? ? ? a0 ? c rlc a rotate a left thru c c ? a7 ? ? ? a0 ? c swap a swap nibbles of a a7?a4 ? a3?a0 sc set c c ? 1, hc ? 1 rc reset c c ? 0, hc ? 0 ifc if c if c is true, do next instruction ifnc if not c if c is not true, do next instruction pop a pop the stack into a sp ? sp+1,a ? [sp] push a push a onto the stack [sp] ? a, sp ? sp?1 vis vector to interrupt service routine pu ? [vu], pl ? [vl] jmpl addr. jump absolute long pc ? ii (ii = 15 bits, 0 to 32k) jmp addr. jump absolute pc9?0 ? i (i = 12 bits) jp disp. jump relative short pc ? pc+r(ris?31to +32, except 1) cop888fh www.national.com 40
instruction set (continued) jsrl addr. jump subroutine long [sp] ? pl, [sp?1] ? pu,sp?2, pc ? ii jsr addr jump subroutine [sp] ? pl, [sp?1] ? pu,sp?2, pc9?0 ? i jid jump indirect pl ? rom (pu,a) ret return from subroutine sp + 2, pl ? [sp], pu ? [sp?1] retsk return and skip sp + 2, pl ? [sp],pu ? [sp?1], skip next instruction reti return from interrupt sp + 2, pl ? [sp],pu ? [sp?1],gie ? 1 intr generate an interrupt [sp] ? pl, [sp?1] ? pu, sp?2, pc ? 0ff nop no operation pc ? pc+1 cop888fh www.national.com 41
instruction execution time most instructions are single byte (with immediate addressing mode instructions taking two bytes). most single byte instructions take one cycle time to execute. skipped instructions require x number of cycles to be skipped, where x equals the number of bytes in the skipped instruction opcode. see the bytes and cycles per instruction table for details. bytes and cycles per instruction the following table shows the number of bytes and cycles for each instruction in the format of byte/cycle. arithmetic and logic instructions [b] direct immed. add 1/1 3/4 2/2 adc 1/1 3/4 2/2 subc 1/1 3/4 2/2 and 1/1 3/4 2/2 or 1/1 3/4 2/2 xor 1/1 3/4 2/2 ifeq 1/1 3/4 2/2 ifne 1/1 3/4 2/2 ifgt 1/1 3/4 2/2 ifbne 1/1 drsz 1/3 sbit 1/1 3/4 rbit 1/1 3/4 ifbit 1/1 3/4 rpnd 1/1 instructions using a & c clra 1/1 inca 1/1 deca 1/1 laid 1/3 dcor 1/1 rrca 1/1 rlca 1/1 swapa 1/1 sc 1/1 rc 1/1 ifc 1/1 ifnc 1/1 pusha 1/3 popa 1/3 andsz 2/2 transfer of control instructions jmpl 3/4 jmp 2/3 jp 1/3 jsrl 3/5 jsr 2/5 jid 1/3 vis 1/5 ret 1/5 retsk 1/5 reti 1/5 intr 1/7 nop 1/1 memory transfer instructions register direct immed. register indirect indirect auto incr. & decr. [b] [x] [b+, b?] [x+, x?] xa, * 1/1 1/3 2/3 1/2 1/3 ld a, * 1/1 1/3 2/3 2/2 1/2 1/3 ld b, imm 1/1 (if b < 16) ld b, imm 2/2 (if b > 15) ld mem, imm 2/2 3/3 2/2 ld reg, imm 2/3 ifeq md, imm 3/3 * = > memory location addressed by b or x or directly. cop888fh www.national.com 42
instruction execution time (continued) opcode table bits 74 f e d c ba9 876 5 4 3 2 1 0 bits 30 jp?15 jp?31 ld 0f0, # i drsz 0f0 rrca rc adc a, # i adc a,[b] ifbit 0,[b] * ld b,0f ifbne 0 jsr 000000ff jmp 000000ff jp+17 intr 0 jp?14 jp?30 ld 0f1, # i drsz 0f1 * sc subc a, # i subc a,[b] ifbit 1,[b] * ld b,0e ifbne 1 jsr 010001ff jmp 010001ff jp+18 jp+2 1 jp?13 jp?29 ld 0f2, # i drsz 0f2 x a,[x+] x a,[b+] ifeq a, # i ifeq a,[b] ifbit 2,[b] * ld b,0d ifbne 2 jsr 020002ff jmp 020002ff jp+19 jp+3 2 jp?12 jp?28 ld 0f3, # i drsz 0f3 x a,[x?] x a,[b?] ifgt a, # i ifgt a,[b] ifbit 3,[b] * ld b,0c ifbne 3 jsr 030003ff jmp 030003ff jp+20 jp+4 3 jp?11 jp?27 ld 0f4, # i drsz 0f4 * laid add a, # i add a,[b] ifbit 4,[b] clra ld b,0b ifbne 4 jsr 040004ff jmp 040004ff jp+21 jp+5 4 jp?10 jp?26 ld 0f5, # i drsz 0f5 * jid and a, # i and a,[b] ifbit 5,[b] swapa ld b,0a ifbne 5 jsr 050005ff jmp 050005ff jp+22 jp+6 5 jp?9 jp?25 ld 0f6, # i drsz 0f6 x a,[x] x a,[b] xor a, # i xor a,[b] ifbit 6,[b] dcora ld b,9 ifbne 6 jsr 060006ff jmp 060006ff jp+23 jp+7 6 jp?8 jp?24 ld 0f7, # i drsz 0f7 ** or a, # i or a,[b] ifbit 7,[b] * ld b,8 ifbne 7 jsr 070007ff jmp 070007ff jp+24 jp+8 7 jp?7 jp?23 ld 0f8, # i drsz 0f8 nop * ld a, # i ifc sbit 0,[b] rbit 0,[b] ld b,7 ifbne 8 jsr 080008ff jmp 080008ff jp+25 jp+9 8 jp?6 jp?22 ld 0f9, # i drsz 0f9 *** ifnc sbit 1,[b] rbit 1,[b] ld b,6 ifbne 9 jsr 090009ff jmp 090009ff jp+26 jp+10 9 jp?5 jp?21 ld 0fa, # i drsz 0fa ld a,[x+] ld a,[b+] ld [b+], # i inca sbit 2,[b] rbit 2,[b] ld b,5 ifbne 0a jsr 0a000aff jmp 0a000aff jp+27 jp+11 a jp?4 jp?20 ld 0fb, # i drsz 0fb ld a,[x?] ld a,[b?] ld [b?], # i deca sbit 3,[b] rbit 3,[b] ld b,4 ifbne 0b jsr 0b000bff jmp 0b000bff jp+28 jp+12 b jp?3 jp?19 ld 0fc, # i drsz 0fc ld md, # i jmpl x a,md * sbit 4,[b] rbit 4,[b] ld b,3 ifbne 0c jsr 0c000cff jmp 0c000cff jp+29 jp+13 c jp?2 jp?18 ld 0fd, # i drsz 0fd dir jsrl ld a,md retsk sbit 5,[b] rbit 5,[b] ld b,2 ifbne 0d jsr 0d000dff jmp 0d000dff jp+30 jp+14 d jp?1 jp?17 ld 0fe, # i drsz 0fe ld a,[x] ld a,[b] ld [b], # i ret sbit 6,[b] rbit 6,[b] ld b,1 ifbne 0e jsr 0e000eff jmp 0e000eff jp+31 jp+15 e jp?0 jp?16 ld 0ff, # i drsz 0ff *** reti sbit 7,[b] rbit 7,[b] ld b,0 ifbne 0f jsr 0f000fff jmp 0f000fff jp+32 jp+16 f where, i is the immediate data md is a directly addressed memory location * is an unused opcode (see following table) cop888fh www.national.com 43
mask options the mask programmable options are shown below. the op- tions are programmed at the same time as the rom pattern submission. option 1: clock configuration = 1 crystal oscillator(cki/10) g7 (cko) is clock generator output to crystal/resonator cki is the clock input = 2 external (cki/io) cko available as g7 input crystal oscillator (cki/10) = 3 single-pin rc controlled oscillator (ck1/10) g7 is available as a halt restart and/or general purpose input option 2: halt = 1 enable halt mode = 2 disable halt mode option 3: bonding options = 1 44-pin plcc = 2 40-pin dip = 3 n/a = 4 28-pin dip = 5 28-pin so the chip can be driven by a clock input on the cki input pin which can be between dc and 10 mhz. the cko output clock is on pin g7 (if clock option = 1 has been selected). the cki input frequency is divided by 10 to produce the in- struction cycle clock (1/t c ). development tools support overview national is engaged with an international community of inde- pendent 3rd party vendors who provide hardware and soft- ware development tool support. through national's interac- tion and guidance, these tools cooperate to form a choice of solutions that fits each developer's needs. this section provides a summary of the tool and develop- ment kits currently available. up-to-date information, selec- tion guides, free tools, demos, updates, and purchase infor- mation can be obtained at our web site at: www.national.com/cop8. summary of tools cop8 evaluation tools cop8nseval: free software evaluation package for windows. a fully integrated evaluation environment for cop8, including versions of wcop8 ide (integrated de- velopment environment), cop8-nsasm, cop8-mlsim, cop8c, driveway ? cop8, manuals, and other cop8 information. cop8mlsim: free instruction level simulator tool for windows. for testing and debugging software instruc- tions only (no i/o or interrupt support). cop8epu: very low cost cop8 evaluation & pro- gramming unit. windows based evaluation and hardware-simulation tool, with cop8 device programmer and erasable samples. includes cop8-nsdev, drive- way cop8 demo, metalink debugger, i/o cables and power supply. cop8eval-icuxx: very low cost evaluation and de- sign test board for cop8acc and cop8sgx families, from icu. real-time environment with add-on a/d, d/a, and eeprom. includes software routines and reference designs. manuals, applications notes, literature: available free from our web site at: www.national.com/cop8. cop8 integrated software/hardware design develop- ment kits cop8-epu: very low cost evaluation & programming unit. windows based development and hardware- simulation tool for copsx/xg families, with cop8 device programmer and samples. includes cop8-nsdev, driveway cop8 demo, metalink debugger, cables and power supply. cop8-dm: moderate cost debug module from metalink. a windows based, real-time in-circuit emulation tool with cop8 device programmer. includes cop8-nsdev, driveway cop8 demo, metalink debugger, power sup- ply, emulation cables and adapters. cop8 development languages and environments cop8-nsasm: free cop8 assembler v5 for win32. macro assembler, linker, and librarian for cop8 software development. supports all cop8 devices. (dos/win16 v4.10.2 available with limited support). (compatible with wcop8 ide, cop8c, and driveway cop8). cop8-nsdev: very low cost software development package for windows. an integrated development envi- ronment for cop8, including wcop8 ide, cop8- nsasm, cop8-mlsim. cop8c: moderately priced c cross-compiler and code development system from byte craft (no code limit). in- cludes bclide (byte craft limited integrated develop- ment environment) for win32, editor, optimizing c cross- compiler, macro cross assembler, bc-linker, and metalink tools support. (dos/sun versions available; compiler is installable under wcop8 ide; compatible with driveway cop8). ewcop8-ks: very low cost ansi c-compiler and em- bedded workbench from iar (kickstart version: cop8sx/fx only with 2k code limit; no fp). a fully inte- grated win32 ide, ansi c-compiler, macro assembler, editor, linker, liberian, c-spy simulator/debugger, plus metalink epu/dm emulator support. ewcop8-as: moderately priced cop8 assembler and embedded workbench from iar (no code limit). a fully in- tegrated win32 ide, macro assembler, editor, linker, li- brarian, and c-spy high-level simulator/debugger with i/o and interrupts support. (upgradeable with optional c-compiler and/or metalink debugger/emulator sup- port). ewcop8-bl: moderately priced ansi c-compiler and embedded workbench from iar (baseline version: all cop8 devices; 4k code limit; no fp). a fully integrated win32 ide, ansi c-compiler, macro assembler, editor, linker, librarian, and c-spy high-level simulator/debugger. (upgradeable; cwcop8-m metalink tools interface sup- port optional). ewcop8: full featured ansi c-compiler and embed- ded workbench for windows from iar (no code limit). a fully integrated win32 ide, ansi c-compiler, macro as- sembler, editor, linker, librarian, and c-spy high-level simulator/debugger. (cwcop8-m metalink tools inter- face support optional). cop888fh www.national.com 44
development tools support (continued) ewcop8-m: full featured ansi c-compiler and embed- ded workbench for windows from iar (no code limit). a fully integrated win32 ide, ansi c-compiler, macro as- sembler, editor, linker, librarian, c-spy high-level simulator/debugger, plus metalink debugger/hardware interface (cwcop8-m). cop8 productivity enhancement tools wcop8 ide: very low cost ide (integrated develop- ment environment) from kkd. supports cop8c, cop8- nsasm, cop8-mlsim, driveway cop8, and metalink debugger under a common windows project manage- ment environment. code development, debug, and emu- lation tools can be launched from the project window framework. driveway-cop8: low cost cop8 peripherals code generation tool from aisys corporation. automatically generates tested and documented c or assembly source code modules containing i/o drivers and interrupt han- dlers for each on-chip peripheral. application specific code can be inserted for customization using the inte- grated editor. (compatible with cop8-nsasm, cop8c, and wcop8 ide.) cop8-utils: free set of cop8 assembly code ex- amples, device drivers, and utilities to speed up code de- velopment. cop8-mlsim: free instruction level simulator tool for windows. for testing and debugging software instruc- tions only (no i/o or interrupt support). cop8 real-time emulation tools cop8-dm: metalink debug module. a moderately priced real-time in-circuit emulation tool, with cop8 de- vice programmer. includes cop8-nsdev, driveway cop8 demo, metalink debugger, power supply, emula- tion cables and adapters. im-cop8: metalink icemaster ? . a full featured, real- time in-circuit emulator for cop8 devices. includes met- alink windows debugger, and power supply. package- specific probes and surface mount adaptors are ordered separately. cop8 device programmer support metalink's epu and debug module include development device programming capability for cop8 devices. third-party programmers and automatic handling equip- ment cover needs from engineering prototype and pilot production, to full production environments. factory programming available for high-volume require- ments. tools ordering numbers for the cop888fh family devices vendor tools order number cost notes national cop8-nseval cop8-nseval free web site download cop8-nsasm cop8-nsasm free included in epu and dm. web site download cop8-mlsim cop8-mlsim free included in epu and dm. web site download cop8-nsdev cop8-nsdev vl included in epu and dm. order cd from website cop8-epu not available for this device cop8-dm contact metalink development devices cop87l84fh cop87l88fh vl 16k otp devices. no windowed devices im-cop8 contact metalink metalink cop8-epu not available for this device cop8-dm dm4-cop8-888fh (10 mhz), plus ps-10, plus dm-cop8/xxx (ie. 40d) m included p/s (ps-10), target cable of choice (dip or plcc; i.e. dm-cop8/40d), 16/20/28/40 dip/so and 44 plcc programming sockets. im-cop8 im-cop8-ad-464 (-220) (10 mhz maximum) h base unit 10 mhz; -220 = 220v; add probe card (required) and target adapter (if needed); included software and manuals im probe card pc-888fh44pw-ad-10 m 10 mhz 40 dip probe card; 2.5v to 6.0v pc-888fh40dw-ad-10 m 10 mhz 44 plcc probe card; 2.5v to 6.0v icu cop8-eval not available for this device kkd wcop8-ide wcop8-ide vl included in epu and dm iar ewcop8-xx see summary above l - h included all software and manuals byte craft cop8c cop8c m included all software and manuals aisys driveway cop8 driveway cop8 l included all software and manuals otp programmers contact vendors l - h for approved programmer listings and vendor information, go to our otp support page at: www.national.com/cop8 cost: free; vl = < $100 ; l = $100 - $300 ; m = $300 - $1k; h = $1k - $3k; vh = $3k - $5k cop888fh www.national.com 45
development tools support (continued) where to get tools tools are ordered directly from the following vendors. please go to the vendor's web site for current listings of distributors. vendor home office electronic sites other main offices aisys u.s.a.: santa clara, ca www.aisysinc.com distributors 1-408-327-8820 info @ aisysinc.com fax: 1-408-327-8830 byte craft u.s.a. www.bytecraft.com distributors 1-519-888-6911 info @ bytecraft.com fax: 1-519-746-6751 iar sweden: uppsala www.iar.se u.s.a.: san francisco +46 18 16 78 00 info @ iar.se 1-415-765-5500 fax: +46 18 16 78 38 info @ iar.com fax: 1-415-765-5503 info @ iarsys.co.uk u.k.: london info @ iar.de +44 171 924 33 34 fax: +44 171 924 53 41 germany: munich +49 89 470 6022 fax: +49 89 470 956 icu sweden: polygonvaegen www.icu.se switzeland: hoehe +46 8 630 11 20 support @ icu.se +41 34 497 28 20 fax: +46 8 630 11 70 support @ icu.ch fax: +41 34 497 28 21 kkd denmark: www.kkd.dk metalink u.s.a.: chandler, az www.metaice.com germany: kirchseeon 1-800-638-2423 sales @ metaice.com 80-91-5696-0 fax: 1-602-926-1198 support @ metaice.com fax: 80-91-2386 bbs: 1-602-962-0013 islanger @ metalink.de www.metalink.de distributors worldwide national u.s.a.: santa clara, ca www.national.com/cop8 europe: +49 (0) 180 530 8585 1-800-272-9959 support @ nsc.com fax: +49 (0) 180 530 8586 fax: 1-800-737-7018 europe.support @ nsc.com distributors worldwide the following companies have approved cop8 program- mers in a variety of configurations. contact your local office or distributor. you can link to their web sites and get the lat- est listing of approved programmers from national's cop8 otp support page at: www.national.com/cop8. advantech; advin; bp microsystems; data i/o; hi-lo sys- tems; ice technology; lloyd research; logical devices; mqp; needhams; phyton; sms; stag programmers; sys- tem general; tribal microsystems; xeltek. customer support complete product information and technical support is avail- able from national's customer response centers, and from our on-line cop8 customer support sites. cop888fh www.national.com 46
physical dimensions inches (millimeters) unless otherwise noted molded so wide body package (m) order number cop684fh-xxx/m, cop884fh-xxx/m or cop984fh-xxx/m ns package number m28b molded dual-in-line package (n) order number cop684fh-xxx/n, cop884fh-xxx/n or cop984fh-xxx/n ns package number n28b cop888fh www.national.com 47
physical dimensions inches (millimeters) unless otherwise noted (continued) molded dual-in-line package (n) order number cop688fh-xxx/n, cop888fh-xxx/n or cop988fh-xxx/n ns package number n40a plastic leaded chip carrier (v) order number cop688fh-xxx/v, cop888fh-xxx/v or cop988fh-xxx/v ns package number v44a cop888fh www.national.com 48
notes life support policy national's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president and general counsel of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. national semiconductor corporation americas tel: 1-800-272-9959 fax: 1-800-737-7018 email: support@nsc.com national semiconductor europe fax: +49 (0) 180-530 85 86 email: europe.support@nsc.com deutsch tel: +49 (0) 69 9508 6208 english tel: +44 (0) 870 24 0 2171 fran?ais tel: +33 (0) 1 41 91 8790 national semiconductor asia pacific customer response group tel: 65-2544466 fax: 65-2504466 email: ap.support@nsc.com national semiconductor japan ltd. tel: 81-3-5639-7560 fax: 81-3-5639-7507 www.national.com cop888fh 8-bit cmos rom based microcontrollers with 12k memory, comparators, usart and hardware multiply/divide national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the righ t at any time without notice to change said circuitry and specifications.

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